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Machine specific IOMMU version (Robert Reif)

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3664 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
blueswir1 2007-11-17 09:04:09 +00:00
parent 2761992d13
commit 7fbfb139ec
3 changed files with 13 additions and 6 deletions
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11
hw/iommu.c
View File

@ -37,7 +37,6 @@ do { printf("IOMMU: " fmt , ##args); } while (0)
#define IOMMU_CTRL (0x0000 >> 2) #define IOMMU_CTRL (0x0000 >> 2)
#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS 0x0f000000 /* Version */ #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
#define IOMMU_VERSION 0x04000000
#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */ #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */ #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */ #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
@ -104,6 +103,7 @@ typedef struct IOMMUState {
target_phys_addr_t addr; target_phys_addr_t addr;
uint32_t regs[IOMMU_NREGS]; uint32_t regs[IOMMU_NREGS];
target_phys_addr_t iostart; target_phys_addr_t iostart;
uint32_t version;
} IOMMUState; } IOMMUState;
static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr) static uint32_t iommu_mem_readw(void *opaque, target_phys_addr_t addr)
@ -158,7 +158,7 @@ static void iommu_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val
break; break;
} }
DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart); DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | IOMMU_VERSION); s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
break; break;
case IOMMU_BASE: case IOMMU_BASE:
s->regs[saddr] = val & IOMMU_BASE_MASK; s->regs[saddr] = val & IOMMU_BASE_MASK;
@ -308,10 +308,11 @@ static void iommu_reset(void *opaque)
memset(s->regs, 0, IOMMU_NREGS * 4); memset(s->regs, 0, IOMMU_NREGS * 4);
s->iostart = 0; s->iostart = 0;
s->regs[IOMMU_CTRL] = IOMMU_VERSION; s->regs[IOMMU_CTRL] = s->version;
s->regs[IOMMU_ARBEN] = IOMMU_MID;
} }
void *iommu_init(target_phys_addr_t addr) void *iommu_init(target_phys_addr_t addr, uint32_t version)
{ {
IOMMUState *s; IOMMUState *s;
int iommu_io_memory; int iommu_io_memory;
@ -321,12 +322,14 @@ void *iommu_init(target_phys_addr_t addr)
return NULL; return NULL;
s->addr = addr; s->addr = addr;
s->version = version;
iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s); iommu_io_memory = cpu_register_io_memory(0, iommu_mem_read, iommu_mem_write, s);
cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory); cpu_register_physical_memory(addr, IOMMU_NREGS * 4, iommu_io_memory);
register_savevm("iommu", addr, 2, iommu_save, iommu_load, s); register_savevm("iommu", addr, 2, iommu_save, iommu_load, s);
qemu_register_reset(iommu_reset, s); qemu_register_reset(iommu_reset, s);
iommu_reset(s);
return s; return s;
} }

6
hw/sun4m.c
View File

@ -72,6 +72,7 @@ struct hwdef {
int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq; int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq; int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
int machine_id; // For NVRAM int machine_id; // For NVRAM
uint32_t iommu_version;
uint32_t intbit_to_level[32]; uint32_t intbit_to_level[32];
}; };
@ -302,7 +303,7 @@ static void *sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
/* allocate RAM */ /* allocate RAM */
cpu_register_physical_memory(0, RAM_size, 0); cpu_register_physical_memory(0, RAM_size, 0);
iommu = iommu_init(hwdef->iommu_base); iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version);
slavio_intctl = slavio_intctl_init(hwdef->intctl_base, slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
hwdef->intctl_base + 0x10000ULL, hwdef->intctl_base + 0x10000ULL,
&hwdef->intbit_to_level[0], &hwdef->intbit_to_level[0],
@ -468,6 +469,7 @@ static const struct hwdef hwdefs[] = {
.me_irq = 30, .me_irq = 30,
.cs_irq = 5, .cs_irq = 5,
.machine_id = 0x80, .machine_id = 0x80,
.iommu_version = 0x04000000,
.intbit_to_level = { .intbit_to_level = {
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
@ -501,6 +503,7 @@ static const struct hwdef hwdefs[] = {
.me_irq = 30, .me_irq = 30,
.cs_irq = -1, .cs_irq = -1,
.machine_id = 0x72, .machine_id = 0x72,
.iommu_version = 0x03000000,
.intbit_to_level = { .intbit_to_level = {
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
@ -534,6 +537,7 @@ static const struct hwdef hwdefs[] = {
.me_irq = 30, .me_irq = 30,
.cs_irq = -1, .cs_irq = -1,
.machine_id = 0x71, .machine_id = 0x71,
.iommu_version = 0x01000000,
.intbit_to_level = { .intbit_to_level = {
2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,

2
vl.h
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@ -1051,7 +1051,7 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine; extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine;
/* iommu.c */ /* iommu.c */
void *iommu_init(target_phys_addr_t addr); void *iommu_init(target_phys_addr_t addr, uint32_t version);
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int is_write); uint8_t *buf, int len, int is_write);
static inline void sparc_iommu_memory_read(void *opaque, static inline void sparc_iommu_memory_read(void *opaque,