target-arm: Rearrange aa32 load and store functions
Stop specializing on TARGET_LONG_BITS == 32; unconditionally allocate a temp and expand with tcg_gen_extu_i32_tl. Split out gen_aa32_addr, gen_aa32_frob64, gen_aa32_ld_i32 and gen_aa32_st_i32 as separate interfaces. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
070e3edcea
commit
7f5616f538
@ -932,145 +932,106 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
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* These functions work like tcg_gen_qemu_{ld,st}* except
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* that the address argument is TCGv_i32 rather than TCGv.
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*/
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#if TARGET_LONG_BITS == 32
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#define DO_GEN_LD(SUFF, OPC, BE32_XOR) \
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static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 addr, int index) \
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{ \
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TCGMemOp opc = (OPC) | s->be_data; \
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/* Not needed for user-mode BE32, where we use MO_BE instead. */ \
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if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
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TCGv addr_be = tcg_temp_new(); \
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tcg_gen_xori_i32(addr_be, addr, BE32_XOR); \
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tcg_gen_qemu_ld_i32(val, addr_be, index, opc); \
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tcg_temp_free(addr_be); \
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return; \
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} \
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tcg_gen_qemu_ld_i32(val, addr, index, opc); \
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}
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#define DO_GEN_ST(SUFF, OPC, BE32_XOR) \
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static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 addr, int index) \
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{ \
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TCGMemOp opc = (OPC) | s->be_data; \
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/* Not needed for user-mode BE32, where we use MO_BE instead. */ \
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if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
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TCGv addr_be = tcg_temp_new(); \
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tcg_gen_xori_i32(addr_be, addr, BE32_XOR); \
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tcg_gen_qemu_st_i32(val, addr_be, index, opc); \
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tcg_temp_free(addr_be); \
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return; \
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} \
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tcg_gen_qemu_st_i32(val, addr, index, opc); \
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}
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static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 addr, int index)
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static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, TCGMemOp op)
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{
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TCGv addr = tcg_temp_new();
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tcg_gen_extu_i32_tl(addr, a32);
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/* Not needed for user-mode BE32, where we use MO_BE instead. */
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if (!IS_USER_ONLY && s->sctlr_b && (op & MO_SIZE) < MO_32) {
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tcg_gen_xori_tl(addr, addr, 4 - (1 << (op & MO_SIZE)));
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}
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return addr;
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}
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static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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int index, TCGMemOp opc)
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{
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TCGv addr = gen_aa32_addr(s, a32, opc);
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tcg_gen_qemu_ld_i32(val, addr, index, opc);
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tcg_temp_free(addr);
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}
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static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
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int index, TCGMemOp opc)
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{
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TCGv addr = gen_aa32_addr(s, a32, opc);
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tcg_gen_qemu_st_i32(val, addr, index, opc);
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tcg_temp_free(addr);
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}
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#define DO_GEN_LD(SUFF, OPC) \
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static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 a32, int index) \
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{ \
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gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
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}
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#define DO_GEN_ST(SUFF, OPC) \
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static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 a32, int index) \
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{ \
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gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
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}
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static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
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{
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TCGMemOp opc = MO_Q | s->be_data;
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tcg_gen_qemu_ld_i64(val, addr, index, opc);
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/* Not needed for user-mode BE32, where we use MO_BE instead. */
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if (!IS_USER_ONLY && s->sctlr_b) {
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tcg_gen_rotri_i64(val, val, 32);
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}
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}
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static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 addr, int index)
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static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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int index, TCGMemOp opc)
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{
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TCGMemOp opc = MO_Q | s->be_data;
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TCGv addr = gen_aa32_addr(s, a32, opc);
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tcg_gen_qemu_ld_i64(val, addr, index, opc);
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gen_aa32_frob64(s, val);
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tcg_temp_free(addr);
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}
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static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 a32, int index)
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{
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gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data);
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}
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static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
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int index, TCGMemOp opc)
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{
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TCGv addr = gen_aa32_addr(s, a32, opc);
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/* Not needed for user-mode BE32, where we use MO_BE instead. */
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if (!IS_USER_ONLY && s->sctlr_b) {
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TCGv_i64 tmp = tcg_temp_new_i64();
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tcg_gen_rotri_i64(tmp, val, 32);
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tcg_gen_qemu_st_i64(tmp, addr, index, opc);
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tcg_temp_free_i64(tmp);
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return;
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} else {
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tcg_gen_qemu_st_i64(val, addr, index, opc);
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}
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tcg_gen_qemu_st_i64(val, addr, index, opc);
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}
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#else
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#define DO_GEN_LD(SUFF, OPC, BE32_XOR) \
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static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 addr, int index) \
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{ \
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TCGMemOp opc = (OPC) | s->be_data; \
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TCGv addr64 = tcg_temp_new(); \
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tcg_gen_extu_i32_i64(addr64, addr); \
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/* Not needed for user-mode BE32, where we use MO_BE instead. */ \
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if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
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tcg_gen_xori_i64(addr64, addr64, BE32_XOR); \
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} \
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tcg_gen_qemu_ld_i32(val, addr64, index, opc); \
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tcg_temp_free(addr64); \
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}
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#define DO_GEN_ST(SUFF, OPC, BE32_XOR) \
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static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
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TCGv_i32 addr, int index) \
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{ \
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TCGMemOp opc = (OPC) | s->be_data; \
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TCGv addr64 = tcg_temp_new(); \
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tcg_gen_extu_i32_i64(addr64, addr); \
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/* Not needed for user-mode BE32, where we use MO_BE instead. */ \
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if (!IS_USER_ONLY && s->sctlr_b && BE32_XOR) { \
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tcg_gen_xori_i64(addr64, addr64, BE32_XOR); \
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} \
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tcg_gen_qemu_st_i32(val, addr64, index, opc); \
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tcg_temp_free(addr64); \
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}
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static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 addr, int index)
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{
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TCGMemOp opc = MO_Q | s->be_data;
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TCGv addr64 = tcg_temp_new();
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tcg_gen_extu_i32_i64(addr64, addr);
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tcg_gen_qemu_ld_i64(val, addr64, index, opc);
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/* Not needed for user-mode BE32, where we use MO_BE instead. */
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if (!IS_USER_ONLY && s->sctlr_b) {
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tcg_gen_rotri_i64(val, val, 32);
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}
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tcg_temp_free(addr64);
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tcg_temp_free(addr);
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}
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static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
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TCGv_i32 addr, int index)
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TCGv_i32 a32, int index)
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{
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TCGMemOp opc = MO_Q | s->be_data;
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TCGv addr64 = tcg_temp_new();
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tcg_gen_extu_i32_i64(addr64, addr);
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/* Not needed for user-mode BE32, where we use MO_BE instead. */
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if (!IS_USER_ONLY && s->sctlr_b) {
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TCGv tmp = tcg_temp_new();
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tcg_gen_rotri_i64(tmp, val, 32);
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tcg_gen_qemu_st_i64(tmp, addr64, index, opc);
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tcg_temp_free(tmp);
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} else {
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tcg_gen_qemu_st_i64(val, addr64, index, opc);
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}
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tcg_temp_free(addr64);
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gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);
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}
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#endif
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DO_GEN_LD(8s, MO_SB, 3)
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DO_GEN_LD(8u, MO_UB, 3)
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DO_GEN_LD(16s, MO_SW, 2)
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DO_GEN_LD(16u, MO_UW, 2)
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DO_GEN_LD(32u, MO_UL, 0)
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DO_GEN_LD(8s, MO_SB)
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DO_GEN_LD(8u, MO_UB)
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DO_GEN_LD(16s, MO_SW)
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DO_GEN_LD(16u, MO_UW)
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DO_GEN_LD(32u, MO_UL)
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/* 'a' variants include an alignment check */
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DO_GEN_LD(16ua, MO_UW | MO_ALIGN, 2)
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DO_GEN_LD(32ua, MO_UL | MO_ALIGN, 0)
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DO_GEN_ST(8, MO_UB, 3)
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DO_GEN_ST(16, MO_UW, 2)
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DO_GEN_ST(32, MO_UL, 0)
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DO_GEN_LD(16ua, MO_UW | MO_ALIGN)
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DO_GEN_LD(32ua, MO_UL | MO_ALIGN)
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DO_GEN_ST(8, MO_UB)
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DO_GEN_ST(16, MO_UW)
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DO_GEN_ST(32, MO_UL)
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static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
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{
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