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Merge with balrog@git.sv.gnu.org:/srv/git/qemu.git

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This commit is contained in:
Andrzej Zaborowski 2009-08-23 17:19:44 +02:00
commit 7ef6e71c59
9 changed files with 73 additions and 59 deletions
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3
cpu-exec.c
View File

@ -485,9 +485,6 @@ int cpu_exec(CPUState *env1)
env->exception_index = env->interrupt_index;
do_interrupt(env);
env->interrupt_index = 0;
#if !defined(CONFIG_USER_ONLY)
cpu_check_irqs(env);
#endif
next_tb = 0;
}
} else if (interrupt_request & CPU_INTERRUPT_TIMER) {

4
def-helper.h
View File

@ -60,13 +60,13 @@
#define dh_retvar_decl0_void void
#define dh_retvar_decl0_i32 TCGv_i32 retval
#define dh_retvar_decl0_i64 TCGv_i64 retval
#define dh_retvar_decl0_ptr TCGv_iptr retval
#define dh_retvar_decl0_ptr TCGv_ptr retval
#define dh_retvar_decl0(t) glue(dh_retvar_decl0_, dh_alias(t))
#define dh_retvar_decl_void
#define dh_retvar_decl_i32 TCGv_i32 retval,
#define dh_retvar_decl_i64 TCGv_i64 retval,
#define dh_retvar_decl_ptr TCGv_iptr retval,
#define dh_retvar_decl_ptr TCGv_ptr retval,
#define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t))
#define dh_retvar_void TCG_CALL_DUMMY_ARG

16
hw/esp.c
View File

@ -115,7 +115,9 @@ struct ESPState {
#define CMD_TI 0x10
#define CMD_ICCS 0x11
#define CMD_MSGACC 0x12
#define CMD_PAD 0x18
#define CMD_SATN 0x1a
#define CMD_SEL 0x41
#define CMD_SELATN 0x42
#define CMD_SELATNS 0x43
#define CMD_ENSEL 0x44
@ -530,15 +532,25 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
s->rregs[ESP_RINTR] = INTR_DC;
s->rregs[ESP_RSEQ] = 0;
break;
case CMD_PAD:
DPRINTF("Transfer padding (%2.2x)\n", val);
s->rregs[ESP_RSTAT] = STAT_TC;
s->rregs[ESP_RINTR] = INTR_FC;
s->rregs[ESP_RSEQ] = 0;
break;
case CMD_SATN:
DPRINTF("Set ATN (%2.2x)\n", val);
break;
case CMD_SEL:
DPRINTF("Select without ATN (%2.2x)\n", val);
handle_satn(s);
break;
case CMD_SELATN:
DPRINTF("Set ATN (%2.2x)\n", val);
DPRINTF("Select with ATN (%2.2x)\n", val);
handle_satn(s);
break;
case CMD_SELATNS:
DPRINTF("Set ATN & stop (%2.2x)\n", val);
DPRINTF("Select with ATN & stop (%2.2x)\n", val);
handle_satn_stop(s);
break;
case CMD_ENSEL:

9
hw/pci-hotplug.c
View File

@ -125,9 +125,8 @@ static PCIDevice *qemu_pci_hot_add_storage(Monitor *mon,
monitor_printf(mon, "Parameter addr not supported\n");
return NULL;
}
} else if (type == IF_VIRTIO) {
monitor_printf(mon, "virtio requires a backing file/device.\n");
return NULL;
} else {
dinfo = NULL;
}
switch (type) {
@ -135,6 +134,10 @@ static PCIDevice *qemu_pci_hot_add_storage(Monitor *mon,
dev = pci_create("lsi53c895a", devaddr);
break;
case IF_VIRTIO:
if (!dinfo) {
monitor_printf(mon, "virtio requires a backing file/device.\n");
return NULL;
}
dev = pci_create("virtio-blk-pci", devaddr);
qdev_prop_set_drive(&dev->qdev, "drive", dinfo);
break;

14
hw/slavio_intctl.c
View File

@ -220,11 +220,14 @@ static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
slavio_intctlm_mem_writel,
};
void slavio_pic_info(Monitor *mon, void *opaque)
void slavio_pic_info(Monitor *mon, DeviceState *dev)
{
SLAVIO_INTCTLState *s = opaque;
SysBusDevice *sd;
SLAVIO_INTCTLState *s;
int i;
sd = sysbus_from_qdev(dev);
s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
for (i = 0; i < MAX_CPUS; i++) {
monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
s->slaves[i].intreg_pending);
@ -233,15 +236,18 @@ void slavio_pic_info(Monitor *mon, void *opaque)
s->intregm_pending, s->intregm_disabled);
}
void slavio_irq_info(Monitor *mon, void *opaque)
void slavio_irq_info(Monitor *mon, DeviceState *dev)
{
#ifndef DEBUG_IRQ_COUNT
monitor_printf(mon, "irq statistic code not compiled.\n");
#else
SLAVIO_INTCTLState *s = opaque;
SysBusDevice *sd;
SLAVIO_INTCTLState *s;
int i;
int64_t count;
sd = sysbus_from_qdev(dev);
s = FROM_SYSBUS(SLAVIO_INTCTLState, sd);
monitor_printf(mon, "IRQ statistics:\n");
for (i = 0; i < 32; i++) {
count = s->irq_count[i];

15
hw/sun4m.c
View File

@ -209,7 +209,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
m48t59_write(nvram, i, image[i]);
}
static void *slavio_intctl;
static DeviceState *slavio_intctl;
void pic_info(Monitor *mon)
{
@ -748,7 +748,6 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
unsigned long kernel_size;
BlockDriverState *fd[MAX_FD];
void *fw_cfg;
DeviceState *dev;
DriveInfo *dinfo;
/* init CPUs */
@ -768,16 +767,16 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
prom_init(hwdef->slavio_base, bios_name);
dev = slavio_intctl_init(hwdef->intctl_base,
hwdef->intctl_base + 0x10000ULL,
cpu_irqs,
7);
slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
hwdef->intctl_base + 0x10000ULL,
cpu_irqs,
7);
for (i = 0; i < 32; i++) {
slavio_irq[i] = qdev_get_gpio_in(dev, i);
slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
}
for (i = 0; i < MAX_CPUS; i++) {
slavio_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
}
if (hwdef->idreg_base) {

4
hw/sun4m.h
View File

@ -23,8 +23,8 @@ static inline void sparc_iommu_memory_write(void *opaque,
}
/* slavio_intctl.c */
void slavio_pic_info(Monitor *mon, void *opaque);
void slavio_irq_info(Monitor *mon, void *opaque);
void slavio_pic_info(Monitor *mon, DeviceState *dev);
void slavio_irq_info(Monitor *mon, DeviceState *dev);
/* sun4c_intctl.c */
void sun4c_pic_info(Monitor *mon, void *opaque);

65
target-sparc/cpu.h
View File

@ -439,6 +439,22 @@ int cpu_sparc_exec(CPUSPARCState *s);
#endif
#ifndef NO_CPU_IO_DEFS
static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
{
if (unlikely(cwp >= env1->nwindows))
cwp -= env1->nwindows;
return cwp;
}
static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
{
if (unlikely(cwp < 0))
cwp += env1->nwindows;
return cwp;
}
#endif
static inline void memcpy32(target_ulong *dst, const target_ulong *src)
{
dst[0] = src[0];
@ -463,43 +479,25 @@ static inline void cpu_set_cwp(CPUSPARCState *env1, int new_cwp)
env1->regwptr = env1->regbase + (new_cwp * 16);
}
static inline int cpu_cwp_inc(CPUSPARCState *env1, int cwp)
{
if (unlikely(cwp >= env1->nwindows))
cwp -= env1->nwindows;
return cwp;
}
/* sun4m.c, sun4u.c */
void cpu_check_irqs(CPUSPARCState *env);
static inline int cpu_cwp_dec(CPUSPARCState *env1, int cwp)
static inline void PUT_PSR(CPUSPARCState *env1, target_ulong val)
{
if (unlikely(cwp < 0))
cwp += env1->nwindows;
return cwp;
}
env1->psr = val & PSR_ICC;
env1->psref = (val & PSR_EF)? 1 : 0;
env1->psrpil = (val & PSR_PIL) >> 8;
#if ((!defined (TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
cpu_check_irqs(env1);
#endif
env1->psrs = (val & PSR_S)? 1 : 0;
env1->psrps = (val & PSR_PS)? 1 : 0;
#if !defined (TARGET_SPARC64)
#define PUT_PSR(env, val) do { int _tmp = val; \
env->psr = _tmp & PSR_ICC; \
env->psref = (_tmp & PSR_EF)? 1 : 0; \
env->psrpil = (_tmp & PSR_PIL) >> 8; \
env->psrs = (_tmp & PSR_S)? 1 : 0; \
env->psrps = (_tmp & PSR_PS)? 1 : 0; \
env->psret = (_tmp & PSR_ET)? 1 : 0; \
cpu_set_cwp(env, _tmp & PSR_CWP); \
CC_OP = CC_OP_FLAGS; \
} while (0)
#else
#define PUT_PSR(env, val) do { int _tmp = val; \
env->psr = _tmp & PSR_ICC; \
env->psref = (_tmp & PSR_EF)? 1 : 0; \
env->psrpil = (_tmp & PSR_PIL) >> 8; \
env->psrs = (_tmp & PSR_S)? 1 : 0; \
env->psrps = (_tmp & PSR_PS)? 1 : 0; \
cpu_set_cwp(env, _tmp & PSR_CWP); \
CC_OP = CC_OP_FLAGS; \
} while (0)
env1->psret = (val & PSR_ET)? 1 : 0;
#endif
cpu_set_cwp(env1, val & PSR_CWP);
env1->cc_op = CC_OP_FLAGS;
}
#ifdef TARGET_SPARC64
#define GET_CCR(env) (((env->xcc >> 20) << 4) | ((env->psr & PSR_ICC) >> 20))
@ -585,9 +583,6 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
#include "cpu-all.h"
#include "exec-all.h"
/* sum4m.c, sun4u.c */
void cpu_check_irqs(CPUSPARCState *env);
#ifdef TARGET_SPARC64
/* sun4u.c */
void cpu_tick_set_count(void *opaque, uint64_t count);

2
target-sparc/translate.c
View File

@ -1134,6 +1134,7 @@ static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
} else {
dc->pc = dc->npc;
dc->npc = target;
tcg_gen_mov_tl(cpu_pc, cpu_npc);
}
} else {
flush_cond(dc, r_cond);
@ -1174,6 +1175,7 @@ static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
} else {
dc->pc = dc->npc;
dc->npc = target;
tcg_gen_mov_tl(cpu_pc, cpu_npc);
}
} else {
flush_cond(dc, r_cond);