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target/ppc: 7xx: Software TLB cleanup

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This code applies only to the 7xx CPUs, so we can remove the switch
statement.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220204173430.1457358-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Fabiano Rosas 2022-02-09 09:08:56 +01:00 committed by Cédric Le Goater
parent 3c3fa438f6
commit 7df40c5414
1 changed files with 6 additions and 20 deletions
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16
target/ppc/excp_helper.c
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@ -745,7 +745,6 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
{ {
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env; CPUPPCState *env = &cpu->env;
int excp_model = env->excp_model;
target_ulong msr, new_msr, vector; target_ulong msr, new_msr, vector;
int srr0, srr1; int srr0, srr1;
@ -904,26 +903,13 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
switch (excp_model) {
case POWERPC_EXCP_6xx:
/* Swap temporary saved registers with GPRs */
if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
new_msr |= (target_ulong)1 << MSR_TGPR;
hreg_swap_gpr_tgpr(env);
}
/* fall through */
case POWERPC_EXCP_7xx:
ppc_excp_debug_sw_tlb(env, excp); ppc_excp_debug_sw_tlb(env, excp);
msr |= env->crf[0] << 28; msr |= env->crf[0] << 28;
msr |= env->error_code; /* key, D/I, S/L bits */ msr |= env->error_code; /* key, D/I, S/L bits */
/* Set way using a LRU mechanism */ /* Set way using a LRU mechanism */
msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
break;
default:
cpu_abort(cs, "Invalid TLB miss exception\n");
break;
}
break; break;
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
case POWERPC_EXCP_SMI: /* System management interrupt */ case POWERPC_EXCP_SMI: /* System management interrupt */