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tcg/aarch64: implement AND/TEST immediate pattern

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add functions to AND/TEST registers with immediate patterns.

Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 51AC9A0C.3090303@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Claudio Fontana 2013-06-12 16:20:22 +01:00 committed by Peter Maydell
parent 36fac14a64
commit 7deea126b2
1 changed files with 34 additions and 0 deletions
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34
tcg/aarch64/tcg-target.c
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@ -580,6 +580,40 @@ static inline void tcg_out_call(TCGContext *s, tcg_target_long target)
}
}
/* encode a logical immediate, mapping user parameter
M=set bits pattern length to S=M-1 */
static inline unsigned int
aarch64_limm(unsigned int m, unsigned int r)
{
assert(m > 0);
return r << 16 | (m - 1) << 10;
}
/* test a register against an immediate bit pattern made of
M set bits rotated right by R.
Examples:
to test a 32/64 reg against 0x00000007, pass M = 3, R = 0.
to test a 32/64 reg against 0x000000ff, pass M = 8, R = 0.
to test a 32bit reg against 0xff000000, pass M = 8, R = 8.
to test a 32bit reg against 0xff0000ff, pass M = 16, R = 8.
*/
static inline void tcg_out_tst(TCGContext *s, int ext, TCGReg rn,
unsigned int m, unsigned int r)
{
/* using TST alias of ANDS XZR, Xn,#bimm64 0x7200001f */
unsigned int base = ext ? 0xf240001f : 0x7200001f;
tcg_out32(s, base | aarch64_limm(m, r) | rn << 5);
}
/* and a register with a bit pattern, similarly to TST, no flags change */
static inline void tcg_out_andi(TCGContext *s, int ext, TCGReg rd, TCGReg rn,
unsigned int m, unsigned int r)
{
/* using AND 0x12000000 */
unsigned int base = ext ? 0x92400000 : 0x12000000;
tcg_out32(s, base | aarch64_limm(m, r) | rn << 5 | rd);
}
static inline void tcg_out_ret(TCGContext *s)
{
/* emit RET { LR } */