target-arm/translate.c: Don't pass CPUARMState around in the decoder
Passing the CPUARMState around in the decoder is a recipe for bugs where we accidentally generate code that depends on CPU state which isn't reflected in the TB flags. Stop doing this and instead use DisasContext as a way to pass around those bits of CPU state which are known to be safe to use. This commit simply removes initial "CPUARMState *env" parameters from various function definitions, and removes the initial "env" argument from the places where those functions are called. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1414524244-20316-5-git-send-email-peter.maydell@linaro.org Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
This commit is contained in:
Peter Maydell
parent
b53d8923a5
commit
7dcc1f894d
@ -834,8 +834,7 @@ static inline void gen_bx(DisasContext *s, TCGv_i32 var)
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/* Variant of store_reg which uses branch&exchange logic when storing
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to r15 in ARM architecture v7 and above. The source must be a temporary
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and will be marked as dead. */
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static inline void store_reg_bx(CPUARMState *env, DisasContext *s,
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int reg, TCGv_i32 var)
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static inline void store_reg_bx(DisasContext *s, int reg, TCGv_i32 var)
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{
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if (reg == 15 && ENABLE_ARCH_7) {
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gen_bx(s, var);
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@ -848,8 +847,7 @@ static inline void store_reg_bx(CPUARMState *env, DisasContext *s,
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* to r15 in ARM architecture v5T and above. This is used for storing
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* the results of a LDR/LDM/POP into r15, and corresponds to the cases
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* in the ARM ARM which use the LoadWritePC() pseudocode function. */
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static inline void store_reg_from_load(CPUARMState *env, DisasContext *s,
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int reg, TCGv_i32 var)
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static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
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{
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if (reg == 15 && ENABLE_ARCH_5) {
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gen_bx(s, var);
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@ -1541,7 +1539,7 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 dest)
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/* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
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(ie. an undefined instruction). */
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static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
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{
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int rd, wrd;
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int rdhi, rdlo, rd0, rd1, i;
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@ -2547,7 +2545,7 @@ static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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/* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
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(ie. an undefined instruction). */
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static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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static int disas_dsp_insn(DisasContext *s, uint32_t insn)
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{
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int acc, rd0, rd1, rdhi, rdlo;
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TCGv_i32 tmp, tmp2;
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@ -2966,7 +2964,7 @@ static const uint8_t fp_decode_rm[] = {
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FPROUNDING_NEGINF,
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};
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static int disas_vfp_v8_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
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{
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uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
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@ -3002,7 +3000,7 @@ static int disas_vfp_v8_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
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/* Disassemble a VFP instruction. Returns nonzero if an error occurred
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(ie. an undefined instruction). */
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static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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{
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uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
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int dp, veclen;
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@ -3039,7 +3037,7 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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/* Encodings with T=1 (Thumb) or unconditional (ARM):
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* only used in v8 and above.
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*/
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return disas_vfp_v8_insn(env, s, insn);
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return disas_vfp_v8_insn(s, insn);
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}
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dp = ((insn & 0xf00) == 0xb00);
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@ -3962,7 +3960,8 @@ static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y)
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}
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/* Return the mask of PSR bits set by a MSR instruction. */
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static uint32_t msr_mask(CPUARMState *env, DisasContext *s, int flags, int spsr) {
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static uint32_t msr_mask(DisasContext *s, int flags, int spsr)
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{
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uint32_t mask;
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mask = 0;
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@ -4312,7 +4311,7 @@ static struct {
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/* Translate a NEON load/store element instruction. Return nonzero if the
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instruction is invalid. */
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static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
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{
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int rd, rn, rm;
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int op;
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@ -5054,7 +5053,7 @@ static const uint8_t neon_2rm_sizes[] = {
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We process data in a mixture of 32-bit and 64-bit chunks.
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Mostly we use 32-bit chunks so we can use normal scalar instructions. */
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static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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{
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int op;
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int q;
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@ -7049,7 +7048,7 @@ static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t ins
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return 0;
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}
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static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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static int disas_coproc_insn(DisasContext *s, uint32_t insn)
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{
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int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
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const ARMCPRegInfo *ri;
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@ -7062,9 +7061,9 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
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return 1;
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}
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if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
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return disas_iwmmxt_insn(env, s, insn);
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return disas_iwmmxt_insn(s, insn);
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} else if (arm_dc_feature(s, ARM_FEATURE_XSCALE)) {
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return disas_dsp_insn(env, s, insn);
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return disas_dsp_insn(s, insn);
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}
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return 1;
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}
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@ -7592,8 +7591,9 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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goto illegal_op;
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}
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if (disas_neon_data_insn(env, s, insn))
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if (disas_neon_data_insn(s, insn)) {
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goto illegal_op;
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}
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return;
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}
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if ((insn & 0x0f100000) == 0x04000000) {
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@ -7602,13 +7602,14 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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goto illegal_op;
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}
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if (disas_neon_ls_insn(env, s, insn))
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if (disas_neon_ls_insn(s, insn)) {
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goto illegal_op;
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}
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return;
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}
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if ((insn & 0x0f000e10) == 0x0e000a00) {
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/* VFP. */
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if (disas_vfp_insn(env, s, insn)) {
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if (disas_vfp_insn(s, insn)) {
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goto illegal_op;
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}
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return;
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@ -7732,7 +7733,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) {
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/* iWMMXt register transfer. */
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if (extract32(s->c15_cpar, 1, 1)) {
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if (!disas_iwmmxt_insn(env, s, insn)) {
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if (!disas_iwmmxt_insn(s, insn)) {
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return;
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}
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}
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@ -7805,8 +7806,10 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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if (shift)
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val = (val >> shift) | (val << (32 - shift));
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i = ((insn & (1 << 22)) != 0);
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if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
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if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i),
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i, val)) {
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goto illegal_op;
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}
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}
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}
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} else if ((insn & 0x0f900000) == 0x01000000
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@ -7821,7 +7824,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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/* PSR = reg */
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tmp = load_reg(s, rm);
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i = ((op1 & 2) != 0);
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if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
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if (gen_set_psr(s, msr_mask(s, (insn >> 16) & 0xf, i), i, tmp))
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goto illegal_op;
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} else {
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/* reg = PSR */
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@ -8059,14 +8062,14 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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if (logic_cc) {
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gen_logic_CC(tmp);
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}
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store_reg_bx(env, s, rd, tmp);
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store_reg_bx(s, rd, tmp);
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break;
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case 0x01:
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tcg_gen_xor_i32(tmp, tmp, tmp2);
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if (logic_cc) {
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gen_logic_CC(tmp);
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}
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store_reg_bx(env, s, rd, tmp);
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store_reg_bx(s, rd, tmp);
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break;
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case 0x02:
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if (set_cc && rd == 15) {
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@ -8082,7 +8085,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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} else {
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tcg_gen_sub_i32(tmp, tmp, tmp2);
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}
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store_reg_bx(env, s, rd, tmp);
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store_reg_bx(s, rd, tmp);
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}
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break;
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case 0x03:
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@ -8091,7 +8094,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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} else {
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tcg_gen_sub_i32(tmp, tmp2, tmp);
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}
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store_reg_bx(env, s, rd, tmp);
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store_reg_bx(s, rd, tmp);
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break;
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case 0x04:
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if (set_cc) {
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@ -8099,7 +8102,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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} else {
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tcg_gen_add_i32(tmp, tmp, tmp2);
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}
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store_reg_bx(env, s, rd, tmp);
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store_reg_bx(s, rd, tmp);
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break;
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case 0x05:
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if (set_cc) {
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@ -8107,7 +8110,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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} else {
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gen_add_carry(tmp, tmp, tmp2);
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}
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store_reg_bx(env, s, rd, tmp);
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store_reg_bx(s, rd, tmp);
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break;
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case 0x06:
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if (set_cc) {
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@ -8115,7 +8118,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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} else {
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gen_sub_carry(tmp, tmp, tmp2);
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}
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store_reg_bx(env, s, rd, tmp);
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store_reg_bx(s, rd, tmp);
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break;
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case 0x07:
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if (set_cc) {
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@ -8123,7 +8126,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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} else {
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gen_sub_carry(tmp, tmp2, tmp);
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}
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store_reg_bx(env, s, rd, tmp);
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store_reg_bx(s, rd, tmp);
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break;
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case 0x08:
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if (set_cc) {
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@ -8156,7 +8159,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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if (logic_cc) {
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gen_logic_CC(tmp);
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}
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store_reg_bx(env, s, rd, tmp);
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store_reg_bx(s, rd, tmp);
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break;
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case 0x0d:
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if (logic_cc && rd == 15) {
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@ -8169,7 +8172,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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if (logic_cc) {
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gen_logic_CC(tmp2);
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}
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store_reg_bx(env, s, rd, tmp2);
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store_reg_bx(s, rd, tmp2);
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}
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break;
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case 0x0e:
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@ -8177,7 +8180,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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if (logic_cc) {
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gen_logic_CC(tmp);
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}
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store_reg_bx(env, s, rd, tmp);
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store_reg_bx(s, rd, tmp);
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break;
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default:
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case 0x0f:
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@ -8185,7 +8188,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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if (logic_cc) {
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gen_logic_CC(tmp2);
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}
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store_reg_bx(env, s, rd, tmp2);
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store_reg_bx(s, rd, tmp2);
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break;
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}
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if (op1 != 0x0f && op1 != 0x0d) {
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@ -8823,7 +8826,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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}
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if (insn & (1 << 20)) {
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/* Complete the load. */
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store_reg_from_load(env, s, rd, tmp);
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store_reg_from_load(s, rd, tmp);
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}
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break;
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case 0x08:
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@ -8886,7 +8889,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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loaded_var = tmp;
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loaded_base = 1;
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} else {
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store_reg_from_load(env, s, i, tmp);
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store_reg_from_load(s, i, tmp);
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}
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} else {
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/* store */
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@ -8969,10 +8972,10 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
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case 0xe:
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if (((insn >> 8) & 0xe) == 10) {
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/* VFP. */
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if (disas_vfp_insn(env, s, insn)) {
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if (disas_vfp_insn(s, insn)) {
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goto illegal_op;
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}
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} else if (disas_coproc_insn(env, s, insn)) {
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} else if (disas_coproc_insn(s, insn)) {
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/* Coprocessor. */
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goto illegal_op;
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}
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@ -9453,7 +9456,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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gen_arm_shift_reg(tmp, op, tmp2, logic_cc);
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if (logic_cc)
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gen_logic_CC(tmp);
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store_reg_bx(env, s, rd, tmp);
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store_reg_bx(s, rd, tmp);
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break;
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case 1: /* Sign/zero extend. */
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tmp = load_reg(s, rm);
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@ -9735,17 +9738,19 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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if (((insn >> 24) & 3) == 3) {
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/* Translate into the equivalent ARM encoding. */
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insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);
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if (disas_neon_data_insn(env, s, insn))
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if (disas_neon_data_insn(s, insn)) {
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goto illegal_op;
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}
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} else if (((insn >> 8) & 0xe) == 10) {
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if (disas_vfp_insn(env, s, insn)) {
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if (disas_vfp_insn(s, insn)) {
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goto illegal_op;
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}
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} else {
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if (insn & (1 << 28))
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goto illegal_op;
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if (disas_coproc_insn (env, s, insn))
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if (disas_coproc_insn(s, insn)) {
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goto illegal_op;
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}
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}
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break;
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case 8: case 9: case 10: case 11:
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@ -9821,7 +9826,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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}
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tmp = load_reg(s, rn);
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if (gen_set_psr(s,
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msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
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msr_mask(s, (insn >> 8) & 0xf, op == 1),
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op == 1, tmp))
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goto illegal_op;
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break;
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@ -10087,8 +10092,9 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
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int writeback = 0;
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int memidx;
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if ((insn & 0x01100000) == 0x01000000) {
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if (disas_neon_ls_insn(env, s, insn))
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if (disas_neon_ls_insn(s, insn)) {
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goto illegal_op;
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}
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break;
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}
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op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
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@ -10784,7 +10790,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
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store_reg(s, 13, addr);
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/* set the new PC value */
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if ((insn & 0x0900) == 0x0900) {
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store_reg_from_load(env, s, 15, tmp);
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store_reg_from_load(s, 15, tmp);
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}
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break;
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