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target/riscv: Use accelerated helper for AES64KS1I

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Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to
implement the first half of the key schedule derivation. This does not
actually involve shifting rows, so clone the same value into all four
columns of the AES vector to counter that operation.

Cc: Richard Henderson <richard.henderson@linaro.org>
Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20230831154118.138727-1-ardb@kernel.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Ard Biesheuvel 2023-08-31 17:41:18 +02:00 committed by Alistair Francis
parent bb0a45e931
commit 7d496bb502
1 changed files with 5 additions and 12 deletions
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17
target/riscv/crypto_helper.c
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@ -148,24 +148,17 @@ target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
uint8_t enc_rnum = rnum; uint8_t enc_rnum = rnum;
uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF; uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
uint8_t rcon_ = 0; AESState t, rc = {};
target_ulong result;
if (enc_rnum != 0xA) { if (enc_rnum != 0xA) {
temp = ror32(temp, 8); /* Rotate right by 8 */ temp = ror32(temp, 8); /* Rotate right by 8 */
rcon_ = round_consts[enc_rnum]; rc.w[0] = rc.w[1] = round_consts[enc_rnum];
} }
temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) | t.w[0] = t.w[1] = t.w[2] = t.w[3] = temp;
((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) | aesenc_SB_SR_AK(&t, &t, &rc, false);
((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0);
temp ^= rcon_; return t.d[0];
result = ((uint64_t)temp << 32) | temp;
return result;
} }
target_ulong HELPER(aes64im)(target_ulong rs1) target_ulong HELPER(aes64im)(target_ulong rs1)