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hw/intc/arm_gicv3_redist: Implement GICR_INMIR0

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Add GICR_INMIR0 register and support access GICR_INMIR0.

Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240407081733.3231820-17-ruanjinjie@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jinjie Ruan 2024-04-19 14:33:02 +01:00 committed by Peter Maydell
parent 0e9f4e8e7b
commit 7c79d98d2e
2 changed files with 20 additions and 0 deletions
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19
hw/intc/arm_gicv3_redist.c
View File

@ -35,6 +35,15 @@ static int gicr_ns_access(GICv3CPUState *cs, int irq)
return extract32(cs->gicr_nsacr, irq * 2, 2);
}
static void gicr_write_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
uint32_t *reg, uint32_t val)
{
/* Helper routine to implement writing to a "set" register */
val &= mask_group(cs, attrs);
*reg = val;
gicv3_redist_update(cs);
}
static void gicr_write_set_bitmap_reg(GICv3CPUState *cs, MemTxAttrs attrs,
uint32_t *reg, uint32_t val)
{
@ -406,6 +415,10 @@ static MemTxResult gicr_readl(GICv3CPUState *cs, hwaddr offset,
*data = value;
return MEMTX_OK;
}
case GICR_INMIR0:
*data = cs->gic->nmi_support ?
gicr_read_bitmap_reg(cs, attrs, cs->gicr_inmir0) : 0;
return MEMTX_OK;
case GICR_ICFGR0:
case GICR_ICFGR1:
{
@ -555,6 +568,12 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset,
gicv3_redist_update(cs);
return MEMTX_OK;
}
case GICR_INMIR0:
if (cs->gic->nmi_support) {
gicr_write_bitmap_reg(cs, attrs, &cs->gicr_inmir0, value);
}
return MEMTX_OK;
case GICR_ICFGR0:
/* Register is all RAZ/WI or RAO/WI bits */
return MEMTX_OK;

1
hw/intc/gicv3_internal.h
View File

@ -110,6 +110,7 @@
#define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04)
#define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00)
#define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
#define GICR_INMIR0 (GICR_SGI_OFFSET + 0x0F80)
/* VLPI redistributor registers, offsets from VLPI_base */
#define GICR_VPROPBASER (GICR_VLPI_OFFSET + 0x70)