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Hexagon (target/hexagon) Reduce manipulation of slot_cancelled

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We only need to track slot for predicated stores and predicated HVX
instructions.

Add arguments to the probe helper functions to indicate if the slot
is predicated.

Here is a simple example of the differences in the TCG code generated:

IN:
0x00400094:  0xf900c102 {       if (P0) R2 = and(R0,R1) }

BEFORE
 ---- 00400094
 mov_i32 slot_cancelled,$0x0
 mov_i32 new_r2,r2
 and_i32 tmp0,p0,$0x1
 brcond_i32 tmp0,$0x0,eq,$L1
 and_i32 tmp0,r0,r1
 mov_i32 new_r2,tmp0
 br $L2
 set_label $L1
 or_i32 slot_cancelled,slot_cancelled,$0x8
 set_label $L2
 mov_i32 r2,new_r2

AFTER
 ---- 00400094
 mov_i32 new_r2,r2
 and_i32 tmp0,p0,$0x1
 brcond_i32 tmp0,$0x0,eq,$L1
 and_i32 tmp0,r0,r1
 mov_i32 new_r2,tmp0
 br $L2
 set_label $L1
 set_label $L2
 mov_i32 r2,new_r2

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-14-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2023-03-06 18:58:27 -08:00
parent e28b77a6b4
commit 7b84fd04bd
8 changed files with 71 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target/hexagon/idef-parser/idef-parser.lex
View File

@ -5,7 +5,7 @@
%{
/*
* Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved.
* Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -312,7 +312,7 @@ STRING_LIT \"(\\.|[^"\\])*\"
"fREAD_PC()" { return PC; }
"USR.LPCFG" { return LPCFG; }
"LOAD_CANCEL(EA)" { return LOAD_CANCEL; }
"STORE_CANCEL(EA)" |
"STORE_CANCEL(EA)" { return STORE_CANCEL; }
"CANCEL" { return CANCEL; }
"N"{LOWER_ID}"N" { yylval->rvalue.type = REGISTER_ARG;
yylval->rvalue.reg.type = DOTNEW;

7
target/hexagon/idef-parser/idef-parser.y
View File

@ -1,6 +1,6 @@
%{
/*
* Copyright(c) 2019-2022 rev.ng Labs Srl. All Rights Reserved.
* Copyright(c) 2019-2023 rev.ng Labs Srl. All Rights Reserved.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -53,7 +53,7 @@
%token ABS CROUND ROUND CIRCADD COUNTONES INC DEC ANDA ORA XORA PLUSPLUS ASL
%token ASR LSR EQ NEQ LTE GTE MIN MAX ANDL FOR ICIRC IF MUN FSCR FCHK SXT
%token ZXT CONSTEXT LOCNT BREV SIGN LOAD STORE PC LPCFG
%token LOAD_CANCEL CANCEL IDENTITY ROTL INSBITS SETBITS EXTRANGE
%token LOAD_CANCEL STORE_CANCEL CANCEL IDENTITY ROTL INSBITS SETBITS EXTRANGE
%token CAST4_8U FAIL CARRY_FROM_ADD ADDSAT64 LSBNEW
%token TYPE_SIZE_T TYPE_INT TYPE_SIGNED TYPE_UNSIGNED TYPE_LONG
@ -412,10 +412,11 @@ cancel_statement : LOAD_CANCEL
{
gen_load_cancel(c, &@1);
}
| CANCEL
| STORE_CANCEL
{
gen_cancel(c, &@1);
}
| CANCEL
;
if_statement : if_stmt

1
target/hexagon/idef-parser/parser-helpers.c
View File

@ -1727,7 +1727,6 @@ void gen_cancel(Context *c, YYLTYPE *locp)
void gen_load_cancel(Context *c, YYLTYPE *locp)
{
gen_cancel(c, locp);
OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n");
OUT(c, locp, "ctx->s1_store_processed = false;\n");
OUT(c, locp, "process_store(ctx, 1);\n");

2
target/hexagon/macros.h
View File

@ -205,7 +205,7 @@ static inline void gen_cancel(uint32_t slot)
#define CANCEL gen_cancel(slot);
#else
#define CANCEL cancel_slot(env, slot)
#define CANCEL do { } while (0)
#endif
#define LOAD_CANCEL(EA) do { CANCEL; } while (0)

32
target/hexagon/op_helper.c
View File

@ -30,6 +30,7 @@
#include "mmvec/mmvec.h"
#include "mmvec/macros.h"
#include "op_helper.h"
#include "translate.h"
#define SF_BIAS 127
#define SF_MANTBITS 23
@ -415,9 +416,10 @@ int32_t HELPER(vacsh_pred)(CPUHexagonState *env,
return PeV;
}
static void probe_store(CPUHexagonState *env, int slot, int mmu_idx)
static void probe_store(CPUHexagonState *env, int slot, int mmu_idx,
bool is_predicated)
{
if (!(env->slot_cancelled & (1 << slot))) {
if (!is_predicated || !(env->slot_cancelled & (1 << slot))) {
size1u_t width = env->mem_log_stores[slot].width;
target_ulong va = env->mem_log_stores[slot].va;
uintptr_t ra = GETPC();
@ -437,9 +439,12 @@ void HELPER(probe_noshuf_load)(CPUHexagonState *env, target_ulong va,
}
/* Called during packet commit when there are two scalar stores */
void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int mmu_idx)
void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int args)
{
probe_store(env, 0, mmu_idx);
int mmu_idx = FIELD_EX32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX);
bool is_predicated =
FIELD_EX32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED);
probe_store(env, 0, mmu_idx, is_predicated);
}
void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx)
@ -486,15 +491,18 @@ void HELPER(probe_hvx_stores)(CPUHexagonState *env, int mmu_idx)
void HELPER(probe_pkt_scalar_hvx_stores)(CPUHexagonState *env, int mask,
int mmu_idx)
{
bool has_st0 = (mask >> 0) & 1;
bool has_st1 = (mask >> 1) & 1;
bool has_hvx_stores = (mask >> 2) & 1;
bool has_st0 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0);
bool has_st1 = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1);
bool has_hvx_stores =
FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES);
bool s0_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED);
bool s1_is_pred = FIELD_EX32(mask, PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED);
if (has_st0) {
probe_store(env, 0, mmu_idx);
probe_store(env, 0, mmu_idx, s0_is_pred);
}
if (has_st1) {
probe_store(env, 1, mmu_idx);
probe_store(env, 1, mmu_idx, s1_is_pred);
}
if (has_hvx_stores) {
HELPER(probe_hvx_stores)(env, mmu_idx);
@ -1444,12 +1452,6 @@ void HELPER(vwhist128qm)(CPUHexagonState *env, int32_t uiV)
}
}
void cancel_slot(CPUHexagonState *env, uint32_t slot)
{
HEX_DEBUG_LOG("Slot %d cancelled\n", slot);
env->slot_cancelled |= (1 << slot);
}
/* These macros can be referenced in the generated helper functions */
#define warn(...) /* Nothing */
#define fatal(...) g_assert_not_reached();

3
target/hexagon/op_helper.h
View File

@ -1,5 +1,5 @@
/*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -19,7 +19,6 @@
#define HEXAGON_OP_HELPER_H
/* Misc functions */
void cancel_slot(CPUHexagonState *env, uint32_t slot);
void write_new_pc(CPUHexagonState *env, bool pkt_has_multi_cof, target_ulong addr);
uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, target_ulong vaddr);

42
target/hexagon/translate.c
View File

@ -248,7 +248,16 @@ static bool check_for_attrib(Packet *pkt, int attrib)
static bool need_slot_cancelled(Packet *pkt)
{
return check_for_attrib(pkt, A_CONDEXEC);
/* We only need slot_cancelled for conditional store and HVX instructions */
for (int i = 0; i < pkt->num_insns; i++) {
uint16_t opcode = pkt->insn[i].opcode;
if (GET_ATTRIB(opcode, A_CONDEXEC) &&
(GET_ATTRIB(opcode, A_STORE) ||
GET_ATTRIB(opcode, A_CVI))) {
return true;
}
}
return false;
}
static bool need_pred_written(Packet *pkt)
@ -845,13 +854,27 @@ static void gen_commit_packet(DisasContext *ctx)
TCGv mask_tcgv;
if (has_store_s0) {
mask |= (1 << 0);
mask =
FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0, 1);
}
if (has_store_s1) {
mask |= (1 << 1);
mask =
FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1);
}
if (has_hvx_store) {
mask |= (1 << 2);
mask =
FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,
HAS_HVX_STORES, 1);
}
if (has_store_s0 && slot_is_predicated(pkt, 0)) {
mask =
FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,
S0_IS_PRED, 1);
}
if (has_store_s1 && slot_is_predicated(pkt, 1)) {
mask =
FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES,
S1_IS_PRED, 1);
}
mask_tcgv = tcg_constant_tl(mask);
gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, mask_tcgv, mem_idx);
@ -861,8 +884,15 @@ static void gen_commit_packet(DisasContext *ctx)
* process_store_log will execute the slot 1 store first,
* so we only have to probe the store in slot 0
*/
TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
gen_helper_probe_pkt_scalar_store_s0(cpu_env, mem_idx);
int args = 0;
args =
FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, ctx->mem_idx);
if (slot_is_predicated(pkt, 0)) {
args =
FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 1);
}
TCGv args_tcgv = tcg_constant_tl(args);
gen_helper_probe_pkt_scalar_store_s0(cpu_env, args_tcgv);
}
process_store_log(ctx);

10
target/hexagon/translate.h
View File

@ -172,4 +172,14 @@ extern TCGv hex_vstore_pending[VSTORES_MAX];
bool is_gather_store_insn(DisasContext *ctx);
void process_store(DisasContext *ctx, int slot_num);
FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, 0, 2)
FIELD(PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 2, 1)
FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0, 0, 1)
FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1, 1)
FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1)
FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED, 3, 1)
FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED, 4, 1)
#endif