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hw/gpio Add GPIO read/write trace event.

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Add GPIO read/write trace event for aspeed model.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220525053444.27228-2-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Jamin Lin 2022-05-25 10:31:33 +02:00 committed by Cédric Le Goater
parent 6827ff20b2
commit 7b1d21a8ba
2 changed files with 43 additions and 15 deletions
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54
hw/gpio/aspeed_gpio.c
View File

@ -15,6 +15,7 @@
#include "qapi/visitor.h"
#include "hw/irq.h"
#include "migration/vmstate.h"
#include "trace.h"
#define GPIOS_PER_GROUP 8
@ -523,11 +524,15 @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size)
uint64_t idx = -1;
const AspeedGPIOReg *reg;
GPIOSets *set;
uint32_t value = 0;
uint64_t debounce_value;
idx = offset >> 2;
if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) {
idx -= GPIO_DEBOUNCE_TIME_1;
return (uint64_t) s->debounce_regs[idx];
debounce_value = (uint64_t) s->debounce_regs[idx];
trace_aspeed_gpio_read(offset, debounce_value);
return debounce_value;
}
reg = &agc->reg_table[idx];
@ -540,38 +545,55 @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size)
set = &s->sets[reg->set_idx];
switch (reg->type) {
case gpio_reg_data_value:
return set->data_value;
value = set->data_value;
break;
case gpio_reg_direction:
return set->direction;
value = set->direction;
break;
case gpio_reg_int_enable:
return set->int_enable;
value = set->int_enable;
break;
case gpio_reg_int_sens_0:
return set->int_sens_0;
value = set->int_sens_0;
break;
case gpio_reg_int_sens_1:
return set->int_sens_1;
value = set->int_sens_1;
break;
case gpio_reg_int_sens_2:
return set->int_sens_2;
value = set->int_sens_2;
break;
case gpio_reg_int_status:
return set->int_status;
value = set->int_status;
break;
case gpio_reg_reset_tolerant:
return set->reset_tol;
value = set->reset_tol;
break;
case gpio_reg_debounce_1:
return set->debounce_1;
value = set->debounce_1;
break;
case gpio_reg_debounce_2:
return set->debounce_2;
value = set->debounce_2;
break;
case gpio_reg_cmd_source_0:
return set->cmd_source_0;
value = set->cmd_source_0;
break;
case gpio_reg_cmd_source_1:
return set->cmd_source_1;
value = set->cmd_source_1;
break;
case gpio_reg_data_read:
return set->data_read;
value = set->data_read;
break;
case gpio_reg_input_mask:
return set->input_mask;
value = set->input_mask;
break;
default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%"
HWADDR_PRIx"\n", __func__, offset);
return 0;
}
trace_aspeed_gpio_read(offset, value);
return value;
}
static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data,
@ -585,6 +607,8 @@ static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data,
GPIOSets *set;
uint32_t cleared;
trace_aspeed_gpio_write(offset, data);
idx = offset >> 2;
if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) {
idx -= GPIO_DEBOUNCE_TIME_1;

4
hw/gpio/trace-events
View File

@ -27,3 +27,7 @@ sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%" P
sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value 0x%" PRIx64
sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
# aspeed_gpio.c
aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64