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MIPS/SPARC patches queue

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- target/mips: Handle lock_user failure in UHI_plog semihosting (Peter Maydell)
 - hw/mips/malta: Turn off x86 specific features of PIIX4 PM (Igor Mammedov)
 - hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses (Peter Maydell)
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Merge tag 'mips-20220809' of https://github.com/philmd/qemu into staging

MIPS/SPARC patches queue

- target/mips: Handle lock_user failure in UHI_plog semihosting (Peter Maydell)
- hw/mips/malta: Turn off x86 specific features of PIIX4 PM (Igor Mammedov)
- hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses (Peter Maydell)

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* tag 'mips-20220809' of https://github.com/philmd/qemu:
  hw/misc/grlib_ahb_apb_pnp: Support 8 and 16 bit accesses
  hw/mips/malta: turn off x86 specific features of PIIX4_PM
  target/mips: Handle lock_user() failure in UHI_plog semihosting call

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-08-08 17:59:27 -07:00
commit 7b06148df8
4 changed files with 20 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
hw/mips/malta.c
View File

@ -1442,6 +1442,14 @@ static const TypeInfo mips_malta_device = {
.instance_init = mips_malta_instance_init,
};
GlobalProperty malta_compat[] = {
{ "PIIX4_PM", "memory-hotplug-support", "off" },
{ "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
{ "PIIX4_PM", "acpi-root-pci-hotplug", "off" },
{ "PIIX4_PM", "x-not-migrate-acpi-index", "true" },
};
const size_t malta_compat_len = G_N_ELEMENTS(malta_compat);
static void mips_malta_machine_init(MachineClass *mc)
{
mc->desc = "MIPS Malta Core LV";
@ -1455,6 +1463,7 @@ static void mips_malta_machine_init(MachineClass *mc)
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
#endif
mc->default_ram_id = "mips_malta.ram";
compat_props_add(mc->compat_props, malta_compat, malta_compat_len);
}
DEFINE_MACHINE("malta", mips_malta_machine_init)

10
hw/misc/grlib_ahb_apb_pnp.c
View File

@ -136,7 +136,8 @@ static uint64_t grlib_ahb_pnp_read(void *opaque, hwaddr offset, unsigned size)
uint32_t val;
val = ahb_pnp->regs[offset >> 2];
trace_grlib_ahb_pnp_read(offset, val);
val = extract32(val, (4 - (offset & 3) - size) * 8, size * 8);
trace_grlib_ahb_pnp_read(offset, size, val);
return val;
}
@ -152,7 +153,7 @@ static const MemoryRegionOps grlib_ahb_pnp_ops = {
.write = grlib_ahb_pnp_write,
.endianness = DEVICE_BIG_ENDIAN,
.impl = {
.min_access_size = 4,
.min_access_size = 1,
.max_access_size = 4,
},
};
@ -247,7 +248,8 @@ static uint64_t grlib_apb_pnp_read(void *opaque, hwaddr offset, unsigned size)
uint32_t val;
val = apb_pnp->regs[offset >> 2];
trace_grlib_apb_pnp_read(offset, val);
val = extract32(val, (4 - (offset & 3) - size) * 8, size * 8);
trace_grlib_apb_pnp_read(offset, size, val);
return val;
}
@ -263,7 +265,7 @@ static const MemoryRegionOps grlib_apb_pnp_ops = {
.write = grlib_apb_pnp_write,
.endianness = DEVICE_BIG_ENDIAN,
.impl = {
.min_access_size = 4,
.min_access_size = 1,
.max_access_size = 4,
},
};

4
hw/misc/trace-events
View File

@ -247,8 +247,8 @@ via1_adb_poll(uint8_t data, const char *vadbint, int status, int index, int size
via1_auxmode(int mode) "setting auxmode to %d"
# grlib_ahb_apb_pnp.c
grlib_ahb_pnp_read(uint64_t addr, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" data:0x%08x"
grlib_apb_pnp_read(uint64_t addr, uint32_t value) "APB PnP read addr:0x%03"PRIx64" data:0x%08x"
grlib_ahb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x"
grlib_apb_pnp_read(uint64_t addr, unsigned size, uint32_t value) "APB PnP read addr:0x%03"PRIx64" size:%u data:0x%08x"
# led.c
led_set_intensity(const char *color, const char *desc, uint8_t intensity_percent) "LED desc:'%s' color:%s intensity: %u%%"

3
target/mips/tcg/sysemu/mips-semi.c
View File

@ -321,6 +321,9 @@ void mips_semihosting(CPUMIPSState *env)
if (use_gdb_syscalls()) {
addr = gpr[29] - str->len;
p = lock_user(VERIFY_WRITE, addr, str->len, 0);
if (!p) {
report_fault(env);
}
memcpy(p, str->str, str->len);
unlock_user(p, addr, str->len);
semihost_sys_write(cs, uhi_cb, 2, addr, str->len);