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target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event

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PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.

Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time SPR_CTRL is written. A small tweak in
pmu_increment_insns() is then needed to only increment this event
if the thread has the run latch.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-8-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Daniel Henrique Barboza 2021-12-17 17:57:18 +01:00 committed by Cédric Le Goater
parent 46d396bde9
commit 7aeac354a6
5 changed files with 42 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target/ppc/cpu.h
View File

@ -303,6 +303,7 @@ typedef enum {
PMU_EVENT_INACTIVE,
PMU_EVENT_CYCLES,
PMU_EVENT_INSTRUCTIONS,
PMU_EVENT_INSN_RUN_LATCH,
} PMUEventType;
/*****************************************************************************/
@ -388,6 +389,9 @@ typedef enum {
#define MMCR1_PMC4SEL_START 56
#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
#define CTRL_RUN PPC_BIT(63)
/* LPCR bits */
#define LPCR_VPM0 PPC_BIT(0)
#define LPCR_VPM1 PPC_BIT(1)

2
target/ppc/cpu_init.c
View File

@ -6182,7 +6182,7 @@ static void register_book3s_ctrl_sprs(CPUPPCState *env)
{
spr_register(env, SPR_CTRL, "SPR_CTRL",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, &spr_write_generic,
SPR_NOACCESS, &spr_write_CTRL,
0x00000000);
spr_register(env, SPR_UCTRL, "SPR_UCTRL",
&spr_read_ureg, SPR_NOACCESS,

27
target/ppc/power8-pmu.c
View File

@ -96,6 +96,15 @@ static PMUEventType pmc_get_event(CPUPPCState *env, int sprn)
evt_type = PMU_EVENT_CYCLES;
}
break;
case 0xFA:
/*
* PMC4SEL = 0xFA is the "instructions completed
* with run latch set" event.
*/
if (sprn == SPR_POWER_PMC4) {
evt_type = PMU_EVENT_INSN_RUN_LATCH;
}
break;
case 0xFE:
/*
* PMC1SEL = 0xFE is the architected PowerISA v3.1
@ -117,7 +126,8 @@ bool pmu_insn_cnt_enabled(CPUPPCState *env)
int sprn;
for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS) {
if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS ||
pmc_get_event(env, sprn) == PMU_EVENT_INSN_RUN_LATCH) {
return true;
}
}
@ -132,11 +142,22 @@ static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns)
/* PMC6 never counts instructions */
for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
if (pmc_get_event(env, sprn) != PMU_EVENT_INSTRUCTIONS) {
PMUEventType evt_type = pmc_get_event(env, sprn);
bool insn_event = evt_type == PMU_EVENT_INSTRUCTIONS ||
evt_type == PMU_EVENT_INSN_RUN_LATCH;
if (pmc_is_inactive(env, sprn) || !insn_event) {
continue;
}
env->spr[sprn] += num_insns;
if (evt_type == PMU_EVENT_INSTRUCTIONS) {
env->spr[sprn] += num_insns;
}
if (evt_type == PMU_EVENT_INSN_RUN_LATCH &&
env->spr[SPR_CTRL] & CTRL_RUN) {
env->spr[sprn] += num_insns;
}
if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL &&
pmc_has_overflow_enabled(env, sprn)) {

1
target/ppc/spr_tcg.h
View File

@ -28,6 +28,7 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn);
void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
void spr_read_lr(DisasContext *ctx, int gprn, int sprn);

12
target/ppc/translate.c
View File

@ -403,6 +403,18 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
spr_store_dump_spr(sprn);
}
void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
{
spr_write_generic(ctx, sprn, gprn);
/*
* SPR_CTRL writes must force a new translation block,
* allowing the PMU to calculate the run latch events with
* more accuracy.
*/
ctx->base.is_jmp = DISAS_EXIT_UPDATE;
}
#if !defined(CONFIG_USER_ONLY)
void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
{