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target/hexagon: Don't use tcg_temp_local_new_*

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Since tcg_temp_new_* is now identical, use those.

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-01-29 14:41:33 -10:00
parent 5f153b12ab
commit 7a819de850
7 changed files with 26 additions and 30 deletions
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8
target/hexagon/README
View File

@ -81,7 +81,7 @@ tcg_funcs_generated.c.inc
Insn *insn,
Packet *pkt)
{
TCGv RdV = tcg_temp_local_new();
TCGv RdV = tcg_temp_new();
const int RdN = insn->regno[0];
TCGv RsV = hex_gpr[insn->regno[1]];
TCGv RtV = hex_gpr[insn->regno[2]];
@ -146,16 +146,16 @@ istruction.
const int VdN = insn->regno[0];
const intptr_t VdV_off =
ctx_future_vreg_off(ctx, VdN, 1, true);
TCGv_ptr VdV = tcg_temp_local_new_ptr();
TCGv_ptr VdV = tcg_temp_new_ptr();
tcg_gen_addi_ptr(VdV, cpu_env, VdV_off);
const int VuN = insn->regno[1];
const intptr_t VuV_off =
vreg_src_off(ctx, VuN);
TCGv_ptr VuV = tcg_temp_local_new_ptr();
TCGv_ptr VuV = tcg_temp_new_ptr();
const int VvN = insn->regno[2];
const intptr_t VvV_off =
vreg_src_off(ctx, VvN);
TCGv_ptr VvV = tcg_temp_local_new_ptr();
TCGv_ptr VvV = tcg_temp_new_ptr();
tcg_gen_addi_ptr(VuV, cpu_env, VuV_off);
tcg_gen_addi_ptr(VvV, cpu_env, VvV_off);
TCGv slot = tcg_constant_tl(insn->slot);

4
target/hexagon/gen_tcg.h
View File

@ -337,7 +337,7 @@
*/
#define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \
do { \
TCGv LSB = tcg_temp_local_new(); \
TCGv LSB = tcg_temp_new(); \
TCGLabel *label = gen_new_label(); \
tcg_gen_movi_tl(EA, 0); \
PRED; \
@ -397,7 +397,7 @@
/* Predicated loads into a register pair */
#define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \
do { \
TCGv LSB = tcg_temp_local_new(); \
TCGv LSB = tcg_temp_new(); \
TCGLabel *label = gen_new_label(); \
tcg_gen_movi_tl(EA, 0); \
PRED; \

18
target/hexagon/gen_tcg_funcs.py
View File

@ -26,18 +26,14 @@ import hex_common
## Helpers for gen_tcg_func
##
def gen_decl_ea_tcg(f, tag):
if ('A_CONDEXEC' in hex_common.attribdict[tag] or
'A_LOAD' in hex_common.attribdict[tag]):
f.write(" TCGv EA = tcg_temp_local_new();\n")
else:
f.write(" TCGv EA = tcg_temp_new();\n")
f.write(" TCGv EA = tcg_temp_new();\n")
def gen_free_ea_tcg(f):
f.write(" tcg_temp_free(EA);\n")
def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
regN="%s%sN" % (regtype,regid)
f.write(" TCGv_i64 %s%sV = tcg_temp_local_new_i64();\n" % \
f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
(regtype, regid))
if (regtype == "C"):
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
@ -56,7 +52,7 @@ def genptr_decl_pair_writable(f, tag, regtype, regid, regno):
def genptr_decl_writable(f, tag, regtype, regid, regno):
regN="%s%sN" % (regtype,regid)
f.write(" TCGv %s%sV = tcg_temp_local_new();\n" % \
f.write(" TCGv %s%sV = tcg_temp_new();\n" % \
(regtype, regid))
if (regtype == "C"):
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
@ -73,7 +69,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
regN="%s%sN" % (regtype,regid)
if (regtype == "R"):
if (regid in {"ss", "tt"}):
f.write(" TCGv_i64 %s%sV = tcg_temp_local_new_i64();\n" % \
f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
(regtype, regid))
f.write(" const int %s = insn->regno[%d];\n" % \
(regN, regno))
@ -96,14 +92,14 @@ def genptr_decl(f, tag, regtype, regid, regno):
print("Bad register parse: ", regtype, regid)
elif (regtype == "C"):
if (regid == "ss"):
f.write(" TCGv_i64 %s%sV = tcg_temp_local_new_i64();\n" % \
f.write(" TCGv_i64 %s%sV = tcg_temp_new_i64();\n" % \
(regtype, regid))
f.write(" const int %s = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regN, regno))
elif (regid == "dd"):
genptr_decl_pair_writable(f, tag, regtype, regid, regno)
elif (regid == "s"):
f.write(" TCGv %s%sV = tcg_temp_local_new();\n" % \
f.write(" TCGv %s%sV = tcg_temp_new();\n" % \
(regtype, regid))
f.write(" const int %s%sN = insn->regno[%d] + HEX_REG_SA0;\n" % \
(regtype, regid, regno))
@ -575,7 +571,7 @@ def genptr_dst_write_opn(f,regtype, regid, tag):
## We produce:
## static void generate_A2_add(DisasContext *ctx)
## {
## TCGv RdV = tcg_temp_local_new();
## TCGv RdV = tcg_temp_new();
## const int RdN = insn->regno[0];
## TCGv RsV = hex_gpr[insn->regno[1]];
## TCGv RtV = hex_gpr[insn->regno[2]];

16
target/hexagon/genptr.c
View File

@ -706,7 +706,7 @@ static void gen_cond_call(DisasContext *ctx, TCGv pred,
TCGCond cond, int pc_off)
{
TCGv next_PC;
TCGv lsb = tcg_temp_local_new();
TCGv lsb = tcg_temp_new();
TCGLabel *skip = gen_new_label();
tcg_gen_andi_tl(lsb, pred, 1);
gen_write_new_pc_pcrel(ctx, pc_off, cond, lsb);
@ -720,7 +720,7 @@ static void gen_cond_call(DisasContext *ctx, TCGv pred,
static void gen_endloop0(DisasContext *ctx)
{
TCGv lpcfg = tcg_temp_local_new();
TCGv lpcfg = tcg_temp_new();
GET_USR_FIELD(USR_LPCFG, lpcfg);
@ -852,7 +852,7 @@ static void gen_sar(TCGv dst, TCGv src, TCGv shift_amt)
/* Bidirectional shift right with saturation */
static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
{
TCGv shift_amt = tcg_temp_local_new();
TCGv shift_amt = tcg_temp_new();
TCGLabel *positive = gen_new_label();
TCGLabel *done = gen_new_label();
@ -876,7 +876,7 @@ static void gen_asr_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
/* Bidirectional shift left with saturation */
static void gen_asl_r_r_sat(TCGv RdV, TCGv RsV, TCGv RtV)
{
TCGv shift_amt = tcg_temp_local_new();
TCGv shift_amt = tcg_temp_new();
TCGLabel *positive = gen_new_label();
TCGLabel *done = gen_new_label();
@ -918,7 +918,7 @@ static void gen_log_vreg_write(DisasContext *ctx, intptr_t srcoff, int num,
intptr_t dstoff;
if (is_predicated) {
TCGv cancelled = tcg_temp_local_new();
TCGv cancelled = tcg_temp_new();
label_end = gen_new_label();
/* Don't do anything if the slot was cancelled */
@ -959,7 +959,7 @@ static void gen_log_qreg_write(intptr_t srcoff, int num, int vnew,
intptr_t dstoff;
if (is_predicated) {
TCGv cancelled = tcg_temp_local_new();
TCGv cancelled = tcg_temp_new();
label_end = gen_new_label();
/* Don't do anything if the slot was cancelled */
@ -1164,10 +1164,10 @@ void gen_satu_i64_ovfl(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width)
/* Implements the fADDSAT64 macro in TCG */
void gen_add_sat_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 sum = tcg_temp_local_new_i64();
TCGv_i64 sum = tcg_temp_new_i64();
TCGv_i64 xor = tcg_temp_new_i64();
TCGv_i64 cond1 = tcg_temp_new_i64();
TCGv_i64 cond2 = tcg_temp_local_new_i64();
TCGv_i64 cond2 = tcg_temp_new_i64();
TCGv_i64 cond3 = tcg_temp_new_i64();
TCGv_i64 mask = tcg_constant_i64(0x8000000000000000ULL);
TCGv_i64 max_pos = tcg_constant_i64(0x7FFFFFFFFFFFFFFFLL);

4
target/hexagon/idef-parser/README.rst
View File

@ -294,9 +294,9 @@ generators the previous declarations are mapped to
::
int var1; -> TCGv_i32 var1 = tcg_temp_local_new_i32();
int var1; -> TCGv_i32 var1 = tcg_temp_new_i32();
int var2 = 0; -> TCGv_i32 var1 = tcg_temp_local_new_i32();
int var2 = 0; -> TCGv_i32 var1 = tcg_temp_new_i32();
tcg_gen_movi_i32(j, ((int64_t) 0ULL));
which are later automatically freed at the end of the function they're declared

4
target/hexagon/idef-parser/parser-helpers.c
View File

@ -322,7 +322,7 @@ HexValue gen_tmp_local(Context *c,
rvalue.is_manual = false;
rvalue.tmp.index = c->inst.tmp_count;
OUT(c, locp, "TCGv_i", &bit_width, " tmp_", &c->inst.tmp_count,
" = tcg_temp_local_new_i", &bit_width, "();\n");
" = tcg_temp_new_i", &bit_width, "();\n");
c->inst.tmp_count++;
return rvalue;
}
@ -554,7 +554,7 @@ void gen_varid_allocate(Context *c,
new_var.signedness = signedness;
EMIT_HEAD(c, "TCGv_%s %s", bit_suffix, varid->var.name->str);
EMIT_HEAD(c, " = tcg_temp_local_new_%s();\n", bit_suffix);
EMIT_HEAD(c, " = tcg_temp_new_%s();\n", bit_suffix);
g_array_append_val(c->inst.allocated, new_var);
}

2
target/hexagon/translate.c
View File

@ -539,7 +539,7 @@ void process_store(DisasContext *ctx, int slot_num)
tcg_temp_free(cancelled);
}
{
TCGv address = tcg_temp_local_new();
TCGv address = tcg_temp_new();
tcg_gen_mov_tl(address, hex_store_addr[slot_num]);
/*