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target-arm queue:

Browse Source 
* Fix VNCR fault detection logic
  * Fix A64 scalar SQSHRN and SQRSHRN
  * Fix incorrect aa64_tidcp1 feature check
  * hw/arm/virt.c: Remove newline from error_report() string
  * hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
  * hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
  * hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
  * hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
  * hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
  * hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
  * arm: various include header cleanups
  * cleanups to allow some files to be built only once
  * fsl-imx6ul: Add various missing unimplemented devices
  * docs/system/arm/virt.rst: Add note on CPU features off by default
  * hw/char/imx_serial: Implement receive FIFO and ageing timer
  * target/xtensa: fix OOB TLB entry access
  * bswap.h: Fix const_le64() macro
  * hw/arm: add PCIe to Freescale i.MX6
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Merge tag 'pull-target-arm-20240126' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Fix VNCR fault detection logic
 * Fix A64 scalar SQSHRN and SQRSHRN
 * Fix incorrect aa64_tidcp1 feature check
 * hw/arm/virt.c: Remove newline from error_report() string
 * hw/arm/musicpal: Convert to qemu_add_kbd_event_handler()
 * hw/arm/allwinner-a10: Unconditionally map the USB Host controllers
 * hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller
 * hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board
 * hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board
 * hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board
 * arm: various include header cleanups
 * cleanups to allow some files to be built only once
 * fsl-imx6ul: Add various missing unimplemented devices
 * docs/system/arm/virt.rst: Add note on CPU features off by default
 * hw/char/imx_serial: Implement receive FIFO and ageing timer
 * target/xtensa: fix OOB TLB entry access
 * bswap.h: Fix const_le64() macro
 * hw/arm: add PCIe to Freescale i.MX6

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# gpg: Signature made Fri 26 Jan 2024 14:32:59 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20240126' of https://git.linaro.org/people/pmaydell/qemu-arm: (36 commits)
  hw/arm: add PCIe to Freescale i.MX6
  target/arm: Fix incorrect aa64_tidcp1 feature check
  bswap.h: Fix const_le64() macro
  target/arm: Fix A64 scalar SQSHRN and SQRSHRN
  hw/char/imx_serial: Implement receive FIFO and ageing timer
  docs/system/arm/virt.rst: Add note on CPU features off by default
  fsl-imx6ul: Add various missing unimplemented devices
  hw/arm: Build various units only once
  target/arm: Move GTimer definitions to new 'gtimer.h' header
  target/arm: Move e2h_access() helper around
  target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header
  hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header
  target/arm: Expose M-profile register bank index definitions
  hw/misc/xlnx-versal-crl: Build it only once
  hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h'
  hw/cpu/a9mpcore: Build it only once
  target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'
  target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header
  target/arm: Create arm_cpu_mp_affinity
  target/arm: Rename arm_cpu_mp_affinity
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2024-01-26 18:16:34 +00:00
commit 7a1dc45af5
73 changed files with 597 additions and 261 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
docs/system/arm/bananapi_m2u.rst
View File

@ -22,7 +22,10 @@ The Banana Pi M2U machine supports the following devices:
* EMAC ethernet
* GMAC ethernet
* Clock Control Unit
* SATA
* TWI (I2C)
* USB 2.0
* Hardware Watchdog
Limitations
"""""""""""
@ -31,9 +34,7 @@ Currently, Banana Pi M2U does *not* support the following features:
- Graphical output via HDMI, GPU and/or the Display Engine
- Audio output
- Hardware Watchdog
- Real Time Clock
- USB 2.0 interfaces
Also see the 'unimplemented' array in the Allwinner R40 SoC module
for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-r40.c``

13
docs/system/arm/virt.rst
View File

@ -69,6 +69,19 @@ Supported guest CPU types:
Note that the default is ``cortex-a15``, so for an AArch64 guest you must
specify a CPU type.
Also, please note that passing ``max`` CPU (i.e. ``-cpu max``) won't
enable all the CPU features for a given ``virt`` machine. Where a CPU
architectural feature requires support in both the CPU itself and in the
wider system (e.g. the MTE feature), it may not be enabled by default,
but instead requires a machine option to enable it.
For example, MTE support must be enabled with ``-machine virt,mte=on``,
as well as by selecting an MTE-capable CPU (e.g., ``max``) with the
``-cpu`` option.
See the machine-specific options below, or check them for a given machine
by passing the ``help`` suboption, like: ``-machine virt-9.0,help``.
Graphics output is available, but unlike the x86 PC machine types
there is no default display device enabled: you should select one from
the Display devices section of "-device help". The recommended option

6
hw/arm/Kconfig
View File

@ -408,13 +408,17 @@ config ALLWINNER_H3
config ALLWINNER_R40
bool
default y if TCG && ARM
select AHCI
select ALLWINNER_SRAMC
select ALLWINNER_A10_PIT
select ALLWINNER_WDT
select AXP2XX_PMU
select SERIAL
select ARM_TIMER
select ARM_GIC
select UNIMP
select USB_OHCI
select USB_EHCI_SYSBUS
select SD
config RASPI
@ -543,6 +547,7 @@ config FSL_IMX31
config FSL_IMX6
bool
imply PCIE_DEVICES
imply I2C_DEVICES
select A9MPCORE
select IMX
@ -551,6 +556,7 @@ config FSL_IMX6
select IMX_USBPHY
select WDT_IMX2
select PL310 # cache controller
select PCI_EXPRESS_DESIGNWARE
select SDHCI
config ASPEED_SOC

50
hw/arm/allwinner-a10.c
View File

@ -26,6 +26,7 @@
#include "hw/boards.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/loader.h"
#include "target/arm/cpu-qom.h"
#define AW_A10_SRAM_A_BASE 0x00000000
#define AW_A10_DRAMC_BASE 0x01c01000
@ -79,15 +80,10 @@ static void aw_a10_init(Object *obj)
object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C);
if (machine_usb(current_machine)) {
int i;
for (i = 0; i < AW_A10_NUM_USB; i++) {
object_initialize_child(obj, "ehci[*]", &s->ehci[i],
TYPE_PLATFORM_EHCI);
object_initialize_child(obj, "ohci[*]", &s->ohci[i],
TYPE_SYSBUS_OHCI);
}
for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
object_initialize_child(obj, "ehci[*]", &s->ehci[i],
TYPE_PLATFORM_EHCI);
object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI);
}
object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I);
@ -165,28 +161,24 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(dev, 1),
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
if (machine_usb(current_machine)) {
int i;
for (size_t i = 0; i < AW_A10_NUM_USB; i++) {
g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
for (i = 0; i < AW_A10_NUM_USB; i++) {
g_autofree char *bus = g_strdup_printf("usb-bus.%d", i);
object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
true, &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
AW_A10_EHCI_BASE + i * 0x8000);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
qdev_get_gpio_in(dev, 39 + i));
object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable",
true, &error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
AW_A10_EHCI_BASE + i * 0x8000);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
qdev_get_gpio_in(dev, 39 + i));
object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
AW_A10_OHCI_BASE + i * 0x8000);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
qdev_get_gpio_in(dev, 64 + i));
}
object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
AW_A10_OHCI_BASE + i * 0x8000);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
qdev_get_gpio_in(dev, 64 + i));
}
/* SD/MMC */

2
hw/arm/allwinner-h3.c
View File

@ -30,6 +30,8 @@
#include "hw/loader.h"
#include "sysemu/sysemu.h"
#include "hw/arm/allwinner-h3.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/gtimer.h"
/* Memory map */
const hwaddr allwinner_h3_memmap[] = {

69
hw/arm/allwinner-r40.c
View File

@ -23,6 +23,7 @@
#include "qemu/bswap.h"
#include "qemu/module.h"
#include "qemu/units.h"
#include "hw/boards.h"
#include "hw/qdev-core.h"
#include "hw/sysbus.h"
#include "hw/char/serial.h"
@ -32,6 +33,8 @@
#include "sysemu/sysemu.h"
#include "hw/arm/allwinner-r40.h"
#include "hw/misc/allwinner-r40-dramc.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/gtimer.h"
/* Memory map */
const hwaddr allwinner_r40_memmap[] = {
@ -45,8 +48,14 @@ const hwaddr allwinner_r40_memmap[] = {
[AW_R40_DEV_MMC1] = 0x01c10000,
[AW_R40_DEV_MMC2] = 0x01c11000,
[AW_R40_DEV_MMC3] = 0x01c12000,
[AW_R40_DEV_AHCI] = 0x01c18000,
[AW_R40_DEV_EHCI1] = 0x01c19000,
[AW_R40_DEV_OHCI1] = 0x01c19400,
[AW_R40_DEV_EHCI2] = 0x01c1c000,
[AW_R40_DEV_OHCI2] = 0x01c1c400,
[AW_R40_DEV_CCU] = 0x01c20000,
[AW_R40_DEV_PIT] = 0x01c20c00,
[AW_R40_DEV_WDT] = 0x01c20c90,
[AW_R40_DEV_UART0] = 0x01c28000,
[AW_R40_DEV_UART1] = 0x01c28400,
[AW_R40_DEV_UART2] = 0x01c28800,
@ -88,10 +97,9 @@ static struct AwR40Unimplemented r40_unimplemented[] = {
{ "usb0-host", 0x01c14000, 4 * KiB },
{ "crypto", 0x01c15000, 4 * KiB },
{ "spi2", 0x01c17000, 4 * KiB },
{ "sata", 0x01c18000, 4 * KiB },
{ "usb1-host", 0x01c19000, 4 * KiB },
{ "usb1-phy", 0x01c19800, 2 * KiB },
{ "sid", 0x01c1b000, 4 * KiB },
{ "usb2-host", 0x01c1c000, 4 * KiB },
{ "usb2-phy", 0x01c1c800, 2 * KiB },
{ "cs1", 0x01c1d000, 4 * KiB },
{ "spi3", 0x01c1f000, 4 * KiB },
{ "rtc", 0x01c20400, 1 * KiB },
@ -181,6 +189,11 @@ enum {
AW_R40_GIC_SPI_MMC2 = 34,
AW_R40_GIC_SPI_MMC3 = 35,
AW_R40_GIC_SPI_EMAC = 55,
AW_R40_GIC_SPI_AHCI = 56,
AW_R40_GIC_SPI_OHCI1 = 64,
AW_R40_GIC_SPI_OHCI2 = 65,
AW_R40_GIC_SPI_EHCI1 = 76,
AW_R40_GIC_SPI_EHCI2 = 78,
AW_R40_GIC_SPI_GMAC = 85,
};
@ -269,6 +282,8 @@ static void allwinner_r40_init(Object *obj)
object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
"clk1-freq");
object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I);
object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU);
for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
@ -276,6 +291,15 @@ static void allwinner_r40_init(Object *obj)
TYPE_AW_SDHOST_SUN50I_A64);
}
object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI);
for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
object_initialize_child(obj, "ehci[*]", &s->ehci[i],
TYPE_PLATFORM_EHCI);
object_initialize_child(obj, "ohci[*]", &s->ohci[i],
TYPE_SYSBUS_OHCI);
}
object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);
object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC);
@ -407,6 +431,40 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]);
/* SATA / AHCI */
sysbus_realize(SYS_BUS_DEVICE(&s->sata), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0,
allwinner_r40_memmap[AW_R40_DEV_AHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_AHCI));
/* USB */
for (size_t i = 0; i < AW_R40_NUM_USB; i++) {
g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i);
object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true,
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
allwinner_r40_memmap[i ? AW_R40_DEV_EHCI2
: AW_R40_DEV_EHCI1]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
qdev_get_gpio_in(DEVICE(&s->gic),
i ? AW_R40_GIC_SPI_EHCI2
: AW_R40_GIC_SPI_EHCI1));
object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus,
&error_fatal);
sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0,
allwinner_r40_memmap[i ? AW_R40_DEV_OHCI2
: AW_R40_DEV_OHCI1]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0,
qdev_get_gpio_in(DEVICE(&s->gic),
i ? AW_R40_GIC_SPI_OHCI2
: AW_R40_GIC_SPI_OHCI1));
}
/* SD/MMC */
for (int i = 0; i < AW_R40_NUM_MMCS; i++) {
qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic),
@ -492,6 +550,11 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_EMAC));
/* WDT */
sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal);
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0,
allwinner_r40_memmap[AW_R40_DEV_WDT], 1);
/* Unimplemented devices */
for (unsigned i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) {
create_unimplemented_device(r40_unimplemented[i].device_name,

2
hw/arm/armv7m.c
View File

@ -21,7 +21,9 @@
#include "qemu/module.h"
#include "qemu/log.h"
#include "target/arm/idau.h"
#include "target/arm/cpu.h"
#include "target/arm/cpu-features.h"
#include "target/arm/cpu-qom.h"
#include "migration/vmstate.h"
/* Bitbanded IO. Each word corresponds to a single bit. */

1
hw/arm/aspeed_ast2400.c
View File

@ -21,6 +21,7 @@
#include "hw/i2c/aspeed_i2c.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "target/arm/cpu-qom.h"
#define ASPEED_SOC_IOMEM_SIZE 0x00200000

1
hw/arm/aspeed_ast2600.c
View File

@ -16,6 +16,7 @@
#include "hw/i2c/aspeed_i2c.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "target/arm/cpu-qom.h"
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
#define ASPEED_SOC_DPMCU_SIZE 0x00040000

2
hw/arm/bcm2836.c
View File

@ -15,6 +15,8 @@
#include "hw/arm/bcm2836.h"
#include "hw/arm/raspi_platform.h"
#include "hw/sysbus.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/gtimer.h"
struct BCM283XClass {
/*< private >*/

1
hw/arm/collie.c
View File

@ -17,7 +17,6 @@
#include "hw/arm/boot.h"
#include "hw/block/flash.h"
#include "exec/address-spaces.h"
#include "cpu.h"
#include "qom/object.h"
#include "qemu/error-report.h"

2
hw/arm/exynos4210.c
View File

@ -23,6 +23,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "exec/tswap.h"
#include "cpu.h"
#include "hw/cpu/a9mpcore.h"
#include "hw/irq.h"
@ -35,6 +36,7 @@
#include "hw/arm/exynos4210.h"
#include "hw/sd/sdhci.h"
#include "hw/usb/hcd-ehci.h"
#include "target/arm/cpu-qom.h"
#define EXYNOS4210_CHIPID_ADDR 0x10000000

1
hw/arm/fsl-imx25.c
View File

@ -28,6 +28,7 @@
#include "sysemu/sysemu.h"
#include "hw/qdev-properties.h"
#include "chardev/char.h"
#include "target/arm/cpu-qom.h"
#define IMX25_ESDHC_CAPABILITIES 0x07e20000

1
hw/arm/fsl-imx31.c
View File

@ -26,6 +26,7 @@
#include "exec/address-spaces.h"
#include "hw/qdev-properties.h"
#include "chardev/char.h"
#include "target/arm/cpu-qom.h"
static void fsl_imx31_init(Object *obj)
{

26
hw/arm/fsl-imx6.c
View File

@ -22,6 +22,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/fsl-imx6.h"
#include "hw/misc/unimp.h"
#include "hw/usb/imx-usb-phy.h"
#include "hw/boards.h"
#include "hw/qdev-properties.h"
@ -29,6 +30,7 @@
#include "chardev/char.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "target/arm/cpu-qom.h"
#define IMX6_ESDHC_CAPABILITIES 0x057834b4
@ -102,6 +104,8 @@ static void fsl_imx6_init(Object *obj)
object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET);
object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
}
static void fsl_imx6_realize(DeviceState *dev, Error **errp)
@ -109,6 +113,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6State *s = FSL_IMX6(dev);
uint16_t i;
qemu_irq irq;
unsigned int smp_cpus = ms->smp.cpus;
if (smp_cpus > FSL_IMX6_NUM_CPUS) {
@ -424,6 +429,27 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
FSL_IMX6_WDOGn_IRQ[i]));
}
/*
* PCIe
*/
sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR);
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE1_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE2_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE3_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
/*
* PCIe PHY
*/
create_unimplemented_device("pcie-phy", FSL_IMX6_PCIe_ADDR,
FSL_IMX6_PCIe_SIZE);
/* ROM memory */
if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom",
FSL_IMX6_ROM_SIZE, errp)) {

31
hw/arm/fsl-imx6ul.c
View File

@ -25,6 +25,7 @@
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "target/arm/cpu-qom.h"
#define NAME_SIZE 20
@ -192,6 +193,36 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR,
FSL_IMX6UL_A7MPCORE_DAP_SIZE);
/*
* MMDC
*/
create_unimplemented_device("a7mpcore-mmdc", FSL_IMX6UL_MMDC_CFG_ADDR,
FSL_IMX6UL_MMDC_CFG_SIZE);
/*
* OCOTP
*/
create_unimplemented_device("a7mpcore-ocotp", FSL_IMX6UL_OCOTP_CTRL_ADDR,
FSL_IMX6UL_OCOTP_CTRL_SIZE);
/*
* QSPI
*/
create_unimplemented_device("a7mpcore-qspi", FSL_IMX6UL_QSPI_ADDR,
FSL_IMX6UL_QSPI_SIZE);
/*
* CAAM
*/
create_unimplemented_device("a7mpcore-qspi", FSL_IMX6UL_CAAM_ADDR,
FSL_IMX6UL_CAAM_SIZE);
/*
* USBMISC
*/
create_unimplemented_device("a7mpcore-usbmisc", FSL_IMX6UL_USBO2_USBMISC_ADDR,
FSL_IMX6UL_USBO2_USBMISC_SIZE);
/*
* GPTs
*/

1
hw/arm/fsl-imx7.c
View File

@ -26,6 +26,7 @@
#include "sysemu/sysemu.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "target/arm/cpu-qom.h"
#define NAME_SIZE 20

1
hw/arm/gumstix.c
View File

@ -44,7 +44,6 @@
#include "hw/boards.h"
#include "exec/address-spaces.h"
#include "sysemu/qtest.h"
#include "cpu.h"
#define CONNEX_FLASH_SIZE (16 * MiB)
#define CONNEX_RAM_SIZE (64 * MiB)

1
hw/arm/highbank.c
View File

@ -36,6 +36,7 @@
#include "qemu/log.h"
#include "qom/object.h"
#include "cpu.h"
#include "target/arm/cpu-qom.h"
#define SMP_BOOT_ADDR 0x100
#define SMP_BOOT_REG 0x40

2
hw/arm/integratorcp.c
View File

@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/boards.h"
@ -28,6 +27,7 @@
#include "hw/sd/sd.h"
#include "qom/object.h"
#include "audio/audio.h"
#include "target/arm/cpu-qom.h"
#define TYPE_INTEGRATOR_CM "integrator_core"
OBJECT_DECLARE_SIMPLE_TYPE(IntegratorCMState, INTEGRATOR_CM)

1
hw/arm/mainstone.c
View File

@ -23,7 +23,6 @@
#include "hw/block/flash.h"
#include "hw/sysbus.h"
#include "exec/address-spaces.h"
#include "cpu.h"
/* Device addresses */
#define MST_FPGA_PHYS 0x08000000

23
hw/arm/meson.build
View File

@ -9,23 +9,14 @@ arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c'))
arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c'))
arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c'))
arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c'))
arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c'))
arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c'))
arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c'))
arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c'))
arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
arm_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
arm_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c'))
arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c'))
arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c'))
arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c'))
arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c'))
arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c'))
arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c'))
@ -33,8 +24,7 @@ arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c'))
arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c'))
arm_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c', 'pxa2xx_gpio.c', 'pxa2xx_pic.c'))
arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c'))
arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c'))
arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c'))
arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c'))
arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c'))
arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c'))
@ -69,8 +59,19 @@ arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c'))
arm_ss.add(when: 'CONFIG_XEN', if_true: files('xen_arm.c'))
system_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c'))
system_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c'))
system_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c'))
system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c'))
system_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c'))
system_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c'))
system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap2.c'))
system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c'))
system_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c'))
system_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c'))
system_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))
system_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c'))
system_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))
system_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))
system_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c'))
hw_arch += {'arm': arm_ss}

133
hw/arm/musicpal.c
View File

@ -12,7 +12,6 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
@ -39,6 +38,7 @@
#include "hw/net/mv88w8618_eth.h"
#include "audio/audio.h"
#include "qemu/error-report.h"
#include "target/arm/cpu-qom.h"
#define MP_MISC_BASE 0x80002000
#define MP_MISC_SIZE 0x00001000
@ -1043,20 +1043,6 @@ static const TypeInfo musicpal_gpio_info = {
};
/* Keyboard codes & masks */
#define KEY_RELEASED 0x80
#define KEY_CODE 0x7f
#define KEYCODE_TAB 0x0f
#define KEYCODE_ENTER 0x1c
#define KEYCODE_F 0x21
#define KEYCODE_M 0x32
#define KEYCODE_EXTENDED 0xe0
#define KEYCODE_UP 0x48
#define KEYCODE_DOWN 0x50
#define KEYCODE_LEFT 0x4b
#define KEYCODE_RIGHT 0x4d
#define MP_KEY_WHEEL_VOL (1 << 0)
#define MP_KEY_WHEEL_VOL_INV (1 << 1)
#define MP_KEY_WHEEL_NAV (1 << 2)
@ -1074,67 +1060,66 @@ struct musicpal_key_state {
SysBusDevice parent_obj;
/*< public >*/
uint32_t kbd_extended;
uint32_t pressed_keys;
qemu_irq out[8];
};
static void musicpal_key_event(void *opaque, int keycode)
static void musicpal_key_event(DeviceState *dev, QemuConsole *src,
InputEvent *evt)
{
musicpal_key_state *s = opaque;
musicpal_key_state *s = MUSICPAL_KEY(dev);
InputKeyEvent *key = evt->u.key.data;
int qcode = qemu_input_key_value_to_qcode(key->key);
uint32_t event = 0;
int i;
if (keycode == KEYCODE_EXTENDED) {
s->kbd_extended = 1;
return;
switch (qcode) {
case Q_KEY_CODE_UP:
event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
break;
case Q_KEY_CODE_DOWN:
event = MP_KEY_WHEEL_NAV;
break;
case Q_KEY_CODE_LEFT:
event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
break;
case Q_KEY_CODE_RIGHT:
event = MP_KEY_WHEEL_VOL;
break;
case Q_KEY_CODE_F:
event = MP_KEY_BTN_FAVORITS;
break;
case Q_KEY_CODE_TAB:
event = MP_KEY_BTN_VOLUME;
break;
case Q_KEY_CODE_RET:
event = MP_KEY_BTN_NAVIGATION;
break;
case Q_KEY_CODE_M:
event = MP_KEY_BTN_MENU;
break;
}
if (s->kbd_extended) {
switch (keycode & KEY_CODE) {
case KEYCODE_UP:
event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV;
break;
case KEYCODE_DOWN:
event = MP_KEY_WHEEL_NAV;
break;
case KEYCODE_LEFT:
event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV;
break;
case KEYCODE_RIGHT:
event = MP_KEY_WHEEL_VOL;
break;
}
} else {
switch (keycode & KEY_CODE) {
case KEYCODE_F:
event = MP_KEY_BTN_FAVORITS;
break;
case KEYCODE_TAB:
event = MP_KEY_BTN_VOLUME;
break;
case KEYCODE_ENTER:
event = MP_KEY_BTN_NAVIGATION;
break;
case KEYCODE_M:
event = MP_KEY_BTN_MENU;
break;
}
/* Do not repeat already pressed buttons */
if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
/*
* We allow repeated wheel-events when the arrow keys are held down,
* but do not repeat already-pressed buttons for the other key inputs.
*/
if (!(event & (MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_VOL))) {
if (key->down && (s->pressed_keys & event)) {
event = 0;
}
}
if (event) {
/* Raise GPIO pin first if repeating a key */
if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) {
if (key->down && (s->pressed_keys & event)) {
for (i = 0; i <= 7; i++) {
if (event & (1 << i)) {
qemu_set_irq(s->out[i], 1);
@ -1143,17 +1128,15 @@ static void musicpal_key_event(void *opaque, int keycode)
}
for (i = 0; i <= 7; i++) {
if (event & (1 << i)) {
qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED));
qemu_set_irq(s->out[i], !key->down);
}
}
if (keycode & KEY_RELEASED) {
s->pressed_keys &= ~event;
} else {
if (key->down) {
s->pressed_keys |= event;
} else {
s->pressed_keys &= ~event;
}
}
s->kbd_extended = 0;
}
static void musicpal_key_init(Object *obj)
@ -1162,20 +1145,27 @@ static void musicpal_key_init(Object *obj)
DeviceState *dev = DEVICE(sbd);
musicpal_key_state *s = MUSICPAL_KEY(dev);
s->kbd_extended = 0;
s->pressed_keys = 0;
qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out));
}
qemu_add_kbd_event_handler(musicpal_key_event, s);
static const QemuInputHandler musicpal_key_handler = {
.name = "musicpal_key",
.mask = INPUT_EVENT_MASK_KEY,
.event = musicpal_key_event,
};
static void musicpal_key_realize(DeviceState *dev, Error **errp)
{
qemu_input_handler_register(dev, &musicpal_key_handler);
}
static const VMStateDescription musicpal_key_vmsd = {
.name = "musicpal_key",
.version_id = 1,
.minimum_version_id = 1,
.version_id = 2,
.minimum_version_id = 2,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(kbd_extended, musicpal_key_state),
VMSTATE_UINT32(pressed_keys, musicpal_key_state),
VMSTATE_END_OF_LIST()
}
@ -1186,6 +1176,7 @@ static void musicpal_key_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &musicpal_key_vmsd;
dc->realize = musicpal_key_realize;
}
static const TypeInfo musicpal_key_info = {

3
hw/arm/npcm7xx.c
View File

@ -26,6 +26,7 @@
#include "qapi/error.h"
#include "qemu/units.h"
#include "sysemu/sysemu.h"
#include "target/arm/cpu-qom.h"
/*
* This covers the whole MMIO space. We'll use this to catch any MMIO accesses
@ -474,7 +475,7 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
/* CPUs */
for (i = 0; i < nc->num_cpus; i++) {
object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
arm_build_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
&error_abort);
object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
NPCM7XX_GIC_CPU_IF_ADDR, &error_abort);

4
hw/arm/nseries.c
View File

@ -1353,9 +1353,7 @@ static void n8x0_init(MachineState *machine,
n8x0_spi_setup(s);
n8x0_dss_setup(s);
n8x0_cbus_setup(s);
if (machine_usb(machine)) {
n8x0_usb_setup(s);
}
n8x0_usb_setup(s);
if (machine->kernel_filename) {
/* Or at the linux loader. */

1
hw/arm/omap1.c
View File

@ -40,6 +40,7 @@
#include "hw/sysbus.h"
#include "qemu/cutils.h"
#include "qemu/bcd.h"
#include "target/arm/cpu-qom.h"
static inline void omap_log_badwidth(const char *funcname, hwaddr addr, int sz)
{

2
hw/arm/omap2.c
View File

@ -21,7 +21,6 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "cpu.h"
#include "exec/address-spaces.h"
#include "sysemu/blockdev.h"
#include "sysemu/qtest.h"
@ -39,6 +38,7 @@
#include "hw/sysbus.h"
#include "hw/boards.h"
#include "audio/audio.h"
#include "target/arm/cpu-qom.h"
/* Enhanced Audio Controller (CODEC only) */
struct omap_eac_s {

1
hw/arm/omap_sx1.c
View File

@ -35,7 +35,6 @@
#include "hw/block/flash.h"
#include "sysemu/qtest.h"
#include "exec/address-spaces.h"
#include "cpu.h"
#include "qemu/cutils.h"
#include "qemu/error-report.h"

1
hw/arm/palm.c
View File

@ -29,7 +29,6 @@
#include "hw/input/tsc2xxx.h"
#include "hw/irq.h"
#include "hw/loader.h"
#include "cpu.h"
#include "qemu/cutils.h"
#include "qom/object.h"
#include "qemu/error-report.h"

1
hw/arm/realview.c
View File

@ -30,6 +30,7 @@
#include "hw/i2c/arm_sbcon_i2c.h"
#include "hw/sd/sd.h"
#include "audio/audio.h"
#include "target/arm/cpu-qom.h"
#define SMP_BOOT_ADDR 0xe0000000
#define SMP_BOOTREG_ADDR 0x10000030

4
hw/arm/sbsa-ref.c
View File

@ -50,6 +50,8 @@
#include "net/net.h"
#include "qapi/qmp/qlist.h"
#include "qom/object.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/gtimer.h"
#define RAMLIMIT_GB 8192
#define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB)
@ -148,7 +150,7 @@ static const int sbsa_ref_irqmap[] = {
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
{
uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
return arm_cpu_mp_affinity(idx, clustersz);
return arm_build_mp_affinity(idx, clustersz);
}
static void sbsa_fdt_add_gic_node(SBSAMachineState *sms)

1
hw/arm/smmuv3-internal.h
View File

@ -21,6 +21,7 @@
#ifndef HW_ARM_SMMUV3_INTERNAL_H
#define HW_ARM_SMMUV3_INTERNAL_H
#include "hw/registerfields.h"
#include "hw/arm/smmu-common.h"
typedef enum SMMUTranslationStatus {

1
hw/arm/spitz.c
View File

@ -33,7 +33,6 @@
#include "hw/adc/max111x.h"
#include "migration/vmstate.h"
#include "exec/address-spaces.h"
#include "cpu.h"
#include "qom/object.h"
#include "audio/audio.h"

2
hw/arm/strongarm.c
View File

@ -28,7 +28,6 @@
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/qdev-properties-system.h"
@ -46,6 +45,7 @@
#include "qemu/cutils.h"
#include "qemu/log.h"
#include "qom/object.h"
#include "target/arm/cpu-qom.h"
//#define DEBUG

2
hw/arm/versatilepb.c
View File

@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
@ -27,6 +26,7 @@
#include "hw/sd/sd.h"
#include "qom/object.h"
#include "audio/audio.h"
#include "target/arm/cpu-qom.h"
#define VERSATILE_FLASH_ADDR 0x34000000
#define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)

2
hw/arm/vexpress.c
View File

@ -24,7 +24,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/arm/primecell.h"
@ -46,6 +45,7 @@
#include "qapi/qmp/qlist.h"
#include "qom/object.h"
#include "audio/audio.h"
#include "target/arm/cpu-qom.h"
#define VEXPRESS_BOARD_ID 0x8e0
#define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024)

4
hw/arm/virt-acpi-build.c
View File

@ -32,7 +32,6 @@
#include "qemu/error-report.h"
#include "trace.h"
#include "hw/core/cpu.h"
#include "target/arm/cpu.h"
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/nvram/fw_cfg_acpi.h"
@ -59,6 +58,7 @@
#include "hw/acpi/ghes.h"
#include "hw/acpi/viot.h"
#include "hw/virtio/virtio-acpi.h"
#include "target/arm/multiprocessing.h"
#define ARM_SPI_BASE 32
@ -720,7 +720,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
build_append_int_noprefix(table_data, vgic_interrupt, 4);
build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/
/* MPIDR */
build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);
build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8);
/* Processor Power Efficiency Class */
build_append_int_noprefix(table_data, 0, 1);
/* Reserved */

15
hw/arm/virt.c
View File

@ -73,7 +73,10 @@
#include "standard-headers/linux/input.h"
#include "hw/arm/smmuv3.h"
#include "hw/acpi/acpi.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/internals.h"
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
#include "hw/acpi/generic_event_device.h"
@ -370,7 +373,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
for (cpu = 0; cpu < smp_cpus; cpu++) {
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
if (armcpu->mp_affinity & ARM_AFF3_MASK) {
if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) {
addr_cells = 2;
break;
}
@ -397,10 +400,10 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
if (addr_cells == 2) {
qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
armcpu->mp_affinity);
arm_cpu_mp_affinity(armcpu));
} else {
qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
armcpu->mp_affinity);
arm_cpu_mp_affinity(armcpu));
}
if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
@ -1676,7 +1679,7 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
clustersz = GICV3_TARGETLIST_BITS;
}
}
return arm_cpu_mp_affinity(idx, clustersz);
return arm_build_mp_affinity(idx, clustersz);
}
static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
@ -1771,8 +1774,8 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
/* Base address of the high IO region */
memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
if (memtop > BIT_ULL(pa_bits)) {
error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
pa_bits, memtop - BIT_ULL(pa_bits));
error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes",
pa_bits, memtop - BIT_ULL(pa_bits));
exit(EXIT_FAILURE);
}
if (base < device_memory_base) {

3
hw/arm/xilinx_zynq.c
View File

@ -18,7 +18,6 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qapi/error.h"
#include "cpu.h"
#include "hw/sysbus.h"
#include "hw/arm/boot.h"
#include "net/net.h"
@ -37,6 +36,8 @@
#include "hw/qdev-clock.h"
#include "sysemu/reset.h"
#include "qom/object.h"
#include "exec/tswap.h"
#include "target/arm/cpu-qom.h"
#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)

5
hw/arm/xlnx-versal-virt.c
View File

@ -16,10 +16,10 @@
#include "hw/boards.h"
#include "hw/sysbus.h"
#include "hw/arm/fdt.h"
#include "cpu.h"
#include "hw/qdev-properties.h"
#include "hw/arm/xlnx-versal.h"
#include "hw/arm/boot.h"
#include "target/arm/multiprocessing.h"
#include "qom/object.h"
#define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt")
@ -107,7 +107,8 @@ static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
qemu_fdt_setprop_cell(s->fdt, name, "reg",
arm_cpu_mp_affinity(armcpu));
if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci");
}

2
hw/arm/xlnx-versal.c
View File

@ -23,6 +23,8 @@
#include "hw/misc/unimp.h"
#include "hw/arm/xlnx-versal.h"
#include "qemu/log.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/gtimer.h"
#define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72")
#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f")

2
hw/arm/xlnx-zynqmp.c
View File

@ -25,6 +25,8 @@
#include "sysemu/kvm.h"
#include "sysemu/sysemu.h"
#include "kvm_arm.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/gtimer.h"
#define GIC_NUM_SPI_INTR 160

1
hw/arm/z2.c
View File

@ -25,7 +25,6 @@
#include "hw/audio/wm8750.h"
#include "audio/audio.h"
#include "exec/address-spaces.h"
#include "cpu.h"
#include "qom/object.h"
#include "qapi/error.h"

102
hw/char/imx_serial.c
View File

@ -26,6 +26,7 @@
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "qemu/fifo32.h"
#ifndef DEBUG_IMX_UART
#define DEBUG_IMX_UART 0
@ -41,10 +42,11 @@
static const VMStateDescription vmstate_imx_serial = {
.name = TYPE_IMX_SERIAL,
.version_id = 2,
.minimum_version_id = 2,
.version_id = 3,
.minimum_version_id = 3,
.fields = (const VMStateField[]) {
VMSTATE_INT32(readbuff, IMXSerialState),
VMSTATE_FIFO32(rx_fifo, IMXSerialState),
VMSTATE_TIMER(ageing_timer, IMXSerialState),
VMSTATE_UINT32(usr1, IMXSerialState),
VMSTATE_UINT32(usr2, IMXSerialState),
VMSTATE_UINT32(ucr1, IMXSerialState),
@ -71,6 +73,10 @@ static void imx_update(IMXSerialState *s)
* following:
*/
usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
/*
* Interrupt if AGTIM is set (ageing timer interrupt in RxFIFO)
*/
usr1 |= (s->ucr2 & UCR2_ATEN) ? (s->usr1 & USR1_AGTIM) : 0;
/*
* Bits that we want in USR2 are not as conveniently laid out,
* unfortunately.
@ -78,15 +84,66 @@ static void imx_update(IMXSerialState *s)
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
/*
* TCEN and TXDC are both bit 3
* ORE and OREN are both bit 1
* RDR and DREN are both bit 0
*/
mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN);
mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN | UCR4_OREN);
usr2 = s->usr2 & mask;
qemu_set_irq(s->irq, usr1 || usr2);
}
static void imx_serial_rx_fifo_push(IMXSerialState *s, uint32_t value)
{
uint32_t pushed_value = value;
if (fifo32_is_full(&s->rx_fifo)) {
/* Set ORE if FIFO is already full */
s->usr2 |= USR2_ORE;
} else {
if (fifo32_num_used(&s->rx_fifo) == FIFO_SIZE - 1) {
/* Set OVRRUN on 32nd character in FIFO */
pushed_value |= URXD_ERR | URXD_OVRRUN;
}
fifo32_push(&s->rx_fifo, pushed_value);
}
}
static uint32_t imx_serial_rx_fifo_pop(IMXSerialState *s)
{
if (fifo32_is_empty(&s->rx_fifo)) {
return 0;
}
return fifo32_pop(&s->rx_fifo);
}
static void imx_serial_rx_fifo_ageing_timer_int(void *opaque)
{
IMXSerialState *s = (IMXSerialState *) opaque;
s->usr1 |= USR1_AGTIM;
imx_update(s);
}
static void imx_serial_rx_fifo_ageing_timer_restart(void *opaque)
{
/*
* Ageing timer starts ticking when
* RX FIFO is non empty and below trigger level.
* Timer is reset if new character is received or
* a FIFO read occurs.
* Timer triggers an interrupt when duration of
* 8 characters has passed (assuming 115200 baudrate).
*/
IMXSerialState *s = (IMXSerialState *) opaque;
if (!(s->usr1 & USR1_RRDY) && !(s->uts1 & UTS1_RXEMPTY)) {
timer_mod_ns(&s->ageing_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + AGE_DURATION_NS);
} else {
timer_del(&s->ageing_timer);
}
}
static void imx_serial_reset(IMXSerialState *s)
{
@ -102,7 +159,9 @@ static void imx_serial_reset(IMXSerialState *s)
s->ucr3 = 0x700;
s->ubmr = 0;
s->ubrc = 4;
s->readbuff = URXD_ERR;
fifo32_reset(&s->rx_fifo);
timer_del(&s->ageing_timer);
}
static void imx_serial_reset_at_boot(DeviceState *dev)
@ -125,20 +184,28 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXSerialState *s = (IMXSerialState *)opaque;
uint32_t c;
uint32_t c, rx_used;
uint8_t rxtl = s->ufcr & TL_MASK;
DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
switch (offset >> 2) {
case 0x0: /* URXD */
c = s->readbuff;
c = imx_serial_rx_fifo_pop(s);
if (!(s->uts1 & UTS1_RXEMPTY)) {
/* Character is valid */
c |= URXD_CHARRDY;
s->usr1 &= ~USR1_RRDY;
s->usr2 &= ~USR2_RDR;
s->uts1 |= UTS1_RXEMPTY;
rx_used = fifo32_num_used(&s->rx_fifo);
/* Clear RRDY if below threshold */
if (rx_used < rxtl) {
s->usr1 &= ~USR1_RRDY;
}
if (rx_used == 0) {
s->usr2 &= ~USR2_RDR;
s->uts1 |= UTS1_RXEMPTY;
}
imx_update(s);
imx_serial_rx_fifo_ageing_timer_restart(s);
qemu_chr_fe_accept_input(&s->chr);
}
return c;
@ -300,19 +367,24 @@ static void imx_serial_write(void *opaque, hwaddr offset,
static int imx_can_receive(void *opaque)
{
IMXSerialState *s = (IMXSerialState *)opaque;
return !(s->usr1 & USR1_RRDY);
return s->ucr2 & UCR2_RXEN && fifo32_num_used(&s->rx_fifo) < FIFO_SIZE;
}
static void imx_put_data(void *opaque, uint32_t value)
{
IMXSerialState *s = (IMXSerialState *)opaque;
uint8_t rxtl = s->ufcr & TL_MASK;
DPRINTF("received char\n");
imx_serial_rx_fifo_push(s, value);
if (fifo32_num_used(&s->rx_fifo) >= rxtl) {
s->usr1 |= USR1_RRDY;
}
imx_serial_rx_fifo_ageing_timer_restart(s);
s->usr1 |= USR1_RRDY;
s->usr2 |= USR2_RDR;
s->uts1 &= ~UTS1_RXEMPTY;
s->readbuff = value;
if (value & URXD_BRK) {
s->usr2 |= USR2_BRCD;
}
@ -345,6 +417,10 @@ static void imx_serial_realize(DeviceState *dev, Error **errp)
{
IMXSerialState *s = IMX_SERIAL(dev);
fifo32_create(&s->rx_fifo, FIFO_SIZE);
timer_init_ns(&s->ageing_timer, QEMU_CLOCK_VIRTUAL,
imx_serial_rx_fifo_ageing_timer_int, s);
DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));
qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,

1
hw/cpu/a15mpcore.c
View File

@ -26,6 +26,7 @@
#include "hw/qdev-properties.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
#include "target/arm/gtimer.h"
static void a15mp_priv_set_irq(void *opaque, int irq, int level)
{

2
hw/cpu/a9mpcore.c
View File

@ -15,7 +15,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/core/cpu.h"
#include "cpu.h"
#include "target/arm/cpu-qom.h"
#define A9_GIC_NUM_PRIORITY_BITS 5

2
hw/cpu/meson.build
View File

@ -2,5 +2,5 @@ system_ss.add(files('core.c', 'cluster.c'))
system_ss.add(when: 'CONFIG_ARM11MPCORE', if_true: files('arm11mpcore.c'))
system_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview_mpcore.c'))
specific_ss.add(when: 'CONFIG_A9MPCORE', if_true: files('a9mpcore.c'))
system_ss.add(when: 'CONFIG_A9MPCORE', if_true: files('a9mpcore.c'))
specific_ss.add(when: 'CONFIG_A15MPCORE', if_true: files('a15mpcore.c'))

2
hw/misc/meson.build
View File

@ -96,8 +96,8 @@ system_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c'))
system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
'xlnx-versal-crl.c',
'xlnx-versal-xramc.c',
'xlnx-versal-pmc-iou-slcr.c',
'xlnx-versal-cfu.c',

5
hw/misc/xlnx-versal-crl.c
View File

@ -19,6 +19,7 @@
#include "hw/resettable.h"
#include "target/arm/arm-powerctl.h"
#include "target/arm/multiprocessing.h"
#include "hw/misc/xlnx-versal-crl.h"
#ifndef XLNX_VERSAL_CRL_ERR_DEBUG
@ -67,9 +68,9 @@ static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu,
bool rst_old, bool rst_new)
{
if (rst_new) {
arm_set_cpu_off(armcpu->mp_affinity);
arm_set_cpu_off(arm_cpu_mp_affinity(armcpu));
} else {
arm_set_cpu_on_and_reset(armcpu->mp_affinity);
arm_set_cpu_on_and_reset(arm_cpu_mp_affinity(armcpu));
}
}

15
include/hw/arm/allwinner-r40.h
View File

@ -22,6 +22,7 @@
#include "qom/object.h"
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/ide/ahci.h"
#include "hw/intc/arm_gic.h"
#include "hw/sd/allwinner-sdhost.h"
#include "hw/misc/allwinner-r40-ccu.h"
@ -30,6 +31,9 @@
#include "hw/i2c/allwinner-i2c.h"
#include "hw/net/allwinner_emac.h"
#include "hw/net/allwinner-sun8i-emac.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/usb/hcd-ehci.h"
#include "hw/watchdog/allwinner-wdt.h"
#include "target/arm/cpu.h"
#include "sysemu/block-backend.h"
@ -44,8 +48,14 @@ enum {
AW_R40_DEV_MMC1,
AW_R40_DEV_MMC2,
AW_R40_DEV_MMC3,
AW_R40_DEV_AHCI,
AW_R40_DEV_EHCI1,
AW_R40_DEV_OHCI1,
AW_R40_DEV_EHCI2,
AW_R40_DEV_OHCI2,
AW_R40_DEV_CCU,
AW_R40_DEV_PIT,
AW_R40_DEV_WDT,
AW_R40_DEV_UART0,
AW_R40_DEV_UART1,
AW_R40_DEV_UART2,
@ -88,6 +98,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40)
* which are currently emulated by the R40 SoC code.
*/
#define AW_R40_NUM_MMCS 4
#define AW_R40_NUM_USB 2
#define AW_R40_NUM_UARTS 8
struct AwR40State {
@ -105,7 +116,11 @@ struct AwR40State {
const hwaddr *memmap;
AwSRAMCState sramc;
AwA10PITState timer;
AwWdtState wdt;
AllwinnerAHCIState sata;
AwSdHostState mmc[AW_R40_NUM_MMCS];
EHCISysBusState ehci[AW_R40_NUM_USB];
OHCISysBusState ohci[AW_R40_NUM_USB];
AwR40ClockCtlState ccu;
AwR40DramCtlState dramc;
AWI2CState i2c0;

44
include/hw/arm/fsl-imx6.h
View File

@ -32,6 +32,7 @@
#include "hw/net/imx_fec.h"
#include "hw/usb/chipidea.h"
#include "hw/usb/imx-usb-phy.h"
#include "hw/pci-host/designware.h"
#include "exec/memory.h"
#include "cpu.h"
#include "qom/object.h"
@ -55,27 +56,28 @@ struct FslIMX6State {
DeviceState parent_obj;
/*< public >*/
ARMCPU cpu[FSL_IMX6_NUM_CPUS];
A9MPPrivState a9mpcore;
IMX6CCMState ccm;
IMX6SRCState src;
IMX7SNVSState snvs;
IMXSerialState uart[FSL_IMX6_NUM_UARTS];
IMXGPTState gpt;
IMXEPITState epit[FSL_IMX6_NUM_EPITS];
IMXI2CState i2c[FSL_IMX6_NUM_I2CS];
IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS];
SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS];
IMXSPIState spi[FSL_IMX6_NUM_ECSPIS];
IMX2WdtState wdt[FSL_IMX6_NUM_WDTS];
IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
ChipideaState usb[FSL_IMX6_NUM_USBS];
IMXFECState eth;
MemoryRegion rom;
MemoryRegion caam;
MemoryRegion ocram;
MemoryRegion ocram_alias;
uint32_t phy_num;
ARMCPU cpu[FSL_IMX6_NUM_CPUS];
A9MPPrivState a9mpcore;
IMX6CCMState ccm;
IMX6SRCState src;
IMX7SNVSState snvs;
IMXSerialState uart[FSL_IMX6_NUM_UARTS];
IMXGPTState gpt;
IMXEPITState epit[FSL_IMX6_NUM_EPITS];
IMXI2CState i2c[FSL_IMX6_NUM_I2CS];
IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS];
SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS];
IMXSPIState spi[FSL_IMX6_NUM_ECSPIS];
IMX2WdtState wdt[FSL_IMX6_NUM_WDTS];
IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS];
ChipideaState usb[FSL_IMX6_NUM_USBS];
IMXFECState eth;
DesignwarePCIEHost pcie;
MemoryRegion rom;
MemoryRegion caam;
MemoryRegion ocram;
MemoryRegion ocram_alias;
uint32_t phy_num;
};

2
include/hw/arm/fsl-imx6ul.h
View File

@ -182,6 +182,8 @@ enum FslIMX6ULMemoryMap {
FSL_IMX6UL_ENET1_ADDR = 0x02188000,
FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
FSL_IMX6UL_USBO2_USBMISC_SIZE = 0x200,
FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000,
FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200,

1
include/hw/arm/xlnx-versal.h
View File

@ -34,6 +34,7 @@
#include "hw/net/xlnx-versal-canfd.h"
#include "hw/misc/xlnx-versal-cfu.h"
#include "hw/misc/xlnx-versal-cframe-reg.h"
#include "target/arm/cpu.h"
#define TYPE_XLNX_VERSAL "xlnx-versal"
OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)

20
include/hw/char/imx_serial.h
View File

@ -21,12 +21,16 @@
#include "hw/sysbus.h"
#include "chardev/char-fe.h"
#include "qom/object.h"
#include "qemu/fifo32.h"
#define TYPE_IMX_SERIAL "imx.serial"
OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
#define FIFO_SIZE 32
#define URXD_CHARRDY (1<<15) /* character read is valid */
#define URXD_ERR (1<<14) /* Character has error */
#define URXD_OVRRUN (1<<13) /* 32nd character in RX FIFO */
#define URXD_FRMERR (1<<12) /* Character has frame error */
#define URXD_BRK (1<<11) /* Break received */
@ -65,11 +69,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
#define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */
#define UCR1_UARTEN (1<<0) /* UART Enable */
#define UCR2_ATEN (1<<3) /* Ageing Timer Enable */
#define UCR2_TXEN (1<<2) /* Transmitter enable */
#define UCR2_RXEN (1<<1) /* Receiver enable */
#define UCR2_SRST (1<<0) /* Reset complete */
#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
#define UCR4_OREN BIT(1) /* Overrun interrupt enable */
#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
#define UCR4_WKEN BIT(7) /* WAKE interrupt enable */
@ -78,13 +84,25 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL)
#define UTS1_TXFULL (1<<4)
#define UTS1_RXFULL (1<<3)
#define TL_MASK 0x3f
/* Bit time in nanoseconds assuming maximum baud rate of 115200 */
#define BIT_TIME_NS 8681
/* Assume 8 bits per character */
#define NUM_BITS 8
/* Ageing timer triggers after 8 characters */
#define AGE_DURATION_NS (8 * NUM_BITS * BIT_TIME_NS)
struct IMXSerialState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
int32_t readbuff;
QEMUTimer ageing_timer;
Fifo32 rx_fifo;
uint32_t usr1;
uint32_t usr2;

2
include/hw/intc/armv7m_nvic.h
View File

@ -10,7 +10,7 @@
#ifndef HW_ARM_ARMV7M_NVIC_H
#define HW_ARM_ARMV7M_NVIC_H
#include "target/arm/cpu.h"
#include "target/arm/cpu-qom.h"
#include "hw/sysbus.h"
#include "hw/timer/armv7m_systick.h"
#include "qom/object.h"

2
include/hw/misc/xlnx-versal-crl.h
View File

@ -11,7 +11,7 @@
#include "hw/sysbus.h"
#include "hw/register.h"
#include "target/arm/cpu.h"
#include "target/arm/cpu-qom.h"
#define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL)

16
include/qemu/bswap.h
View File

@ -145,14 +145,14 @@ CPU_CONVERT(le, 64, uint64_t)
*/
#if HOST_BIG_ENDIAN
# define const_le64(_x) \
((((_x) & 0x00000000000000ffU) << 56) | \
(((_x) & 0x000000000000ff00U) << 40) | \
(((_x) & 0x0000000000ff0000U) << 24) | \
(((_x) & 0x00000000ff000000U) << 8) | \
(((_x) & 0x000000ff00000000U) >> 8) | \
(((_x) & 0x0000ff0000000000U) >> 24) | \
(((_x) & 0x00ff000000000000U) >> 40) | \
(((_x) & 0xff00000000000000U) >> 56))
((((_x) & 0x00000000000000ffULL) << 56) | \
(((_x) & 0x000000000000ff00ULL) << 40) | \
(((_x) & 0x0000000000ff0000ULL) << 24) | \
(((_x) & 0x00000000ff000000ULL) << 8) | \
(((_x) & 0x000000ff00000000ULL) >> 8) | \
(((_x) & 0x0000ff0000000000ULL) >> 24) | \
(((_x) & 0x00ff000000000000ULL) >> 40) | \
(((_x) & 0xff00000000000000ULL) >> 56))
# define const_le32(_x) \
((((_x) & 0x000000ffU) << 24) | \
(((_x) & 0x0000ff00U) << 8) | \

3
target/arm/arm-powerctl.c
View File

@ -16,6 +16,7 @@
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "sysemu/tcg.h"
#include "target/arm/multiprocessing.h"
#ifndef DEBUG_ARM_POWERCTL
#define DEBUG_ARM_POWERCTL 0
@ -37,7 +38,7 @@ CPUState *arm_get_cpu_by_id(uint64_t id)
CPU_FOREACH(cpu) {
ARMCPU *armcpu = ARM_CPU(cpu);
if (armcpu->mp_affinity == id) {
if (arm_cpu_mp_affinity(armcpu) == id) {
return cpu;
}
}

3
target/arm/cpregs.h
View File

@ -21,6 +21,9 @@
#ifndef TARGET_ARM_CPREGS_H
#define TARGET_ARM_CPREGS_H
#include "hw/registerfields.h"
#include "target/arm/kvm-consts.h"
/*
* ARMCPRegInfo type field bits:
*/

4
target/arm/cpu-features.h
View File

@ -20,6 +20,8 @@
#ifndef TARGET_ARM_FEATURES_H
#define TARGET_ARM_FEATURES_H
#include "hw/registerfields.h"
/*
* Naming convention for isar_feature functions:
* Functions which test 32-bit ID registers should have _aa32_ in
@ -771,7 +773,7 @@ static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0;
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) != 0;
}
static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)

24
target/arm/cpu-qom.h
View File

@ -33,4 +33,28 @@ typedef struct AArch64CPUClass AArch64CPUClass;
DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
TYPE_AARCH64_CPU)
#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
/* Meanings of the ARMCPU object's four inbound GPIO lines */
#define ARM_CPU_IRQ 0
#define ARM_CPU_FIQ 1
#define ARM_CPU_VIRQ 2
#define ARM_CPU_VFIQ 3
/* For M profile, some registers are banked secure vs non-secure;
* these are represented as a 2-element array where the first element
* is the non-secure copy and the second is the secure copy.
* When the CPU does not have implement the security extension then
* only the first element is used.
* This means that the copy for the current security state can be
* accessed via env->registerfield[env->v7m.secure] (whether the security
* extension is implemented or not).
*/
enum {
M_REG_NS = 0,
M_REG_S = 1,
M_REG_NUM_BANKS = 2,
};
#endif

13
target/arm/cpu.c
View File

@ -48,6 +48,8 @@
#include "disas/capstone.h"
#include "fpu/softfloat.h"
#include "cpregs.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/gtimer.h"
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
@ -1307,13 +1309,18 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz)
{
uint32_t Aff1 = idx / clustersz;
uint32_t Aff0 = idx % clustersz;
return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
}
uint64_t arm_cpu_mp_affinity(ARMCPU *cpu)
{
return cpu->mp_affinity;
}
static void arm_cpu_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@ -2113,8 +2120,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* so these bits always RAZ.
*/
if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
ARM_DEFAULT_CPUS_PER_CLUSTER);
cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index,
ARM_DEFAULT_CPUS_PER_CLUSTER);
}
if (cpu->reset_hivecs) {

34
target/arm/cpu.h
View File

@ -26,6 +26,8 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qapi/qapi-types-common.h"
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
@ -72,21 +74,6 @@
#define ARMV7M_EXCP_PENDSV 14
#define ARMV7M_EXCP_SYSTICK 15
/* For M profile, some registers are banked secure vs non-secure;
* these are represented as a 2-element array where the first element
* is the non-secure copy and the second is the secure copy.
* When the CPU does not have implement the security extension then
* only the first element is used.
* This means that the copy for the current security state can be
* accessed via env->registerfield[env->v7m.secure] (whether the security
* extension is implemented or not).
*/
enum {
M_REG_NS = 0,
M_REG_S = 1,
M_REG_NUM_BANKS = 2,
};
/* ARM-specific interrupt pending bits. */
#define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
@ -107,12 +94,6 @@ enum {
#define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
#endif
/* Meanings of the ARMCPU object's four inbound GPIO lines */
#define ARM_CPU_IRQ 0
#define ARM_CPU_FIQ 1
#define ARM_CPU_VIRQ 2
#define ARM_CPU_VFIQ 3
/* ARM-specific extra insn start words:
* 1: Conditional execution bits
* 2: Partial exception syndrome for data aborts
@ -160,13 +141,6 @@ typedef struct ARMGenericTimer {
uint64_t ctl; /* Timer Control register */
} ARMGenericTimer;
#define GTIMER_PHYS 0
#define GTIMER_VIRT 1
#define GTIMER_HYP 2
#define GTIMER_SEC 3
#define GTIMER_HYPVIRT 4
#define NUM_GTIMERS 5
#define VTCR_NSW (1u << 29)
#define VTCR_NSA (1u << 30)
#define VSTCR_SW VTCR_NSW
@ -1171,7 +1145,7 @@ void arm_cpu_post_init(Object *obj);
(ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK)
#define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK)
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz);
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_arm_cpu;
@ -2836,8 +2810,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
#define ARM_CPUID_TI915T 0x54029152
#define ARM_CPUID_TI925T 0x54029252
#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU

21
target/arm/gtimer.h Normal file
View File

@ -0,0 +1,21 @@
/*
* ARM generic timer definitions for Arm A-class CPU
*
* Copyright (c) 2003 Fabrice Bellard
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
#ifndef TARGET_ARM_GTIMER_H
#define TARGET_ARM_GTIMER_H
enum {
GTIMER_PHYS = 0,
GTIMER_VIRT = 1,
GTIMER_HYP = 2,
GTIMER_SEC = 3,
GTIMER_HYPVIRT = 4,
#define NUM_GTIMERS 5
};
#endif

30
target/arm/helper.c
View File

@ -30,6 +30,7 @@
#include "semihosting/common-semi.h"
#endif
#include "cpregs.h"
#include "target/arm/gtimer.h"
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
@ -3345,20 +3346,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
},
};
static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
if (arm_current_el(env) == 1) {
/* This must be a FEAT_NV access */
/* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
return CP_ACCESS_OK;
}
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
}
#else
/*
@ -6546,6 +6533,21 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
};
#ifndef CONFIG_USER_ONLY
static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
if (arm_current_el(env) == 1) {
/* This must be a FEAT_NV access */
/* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */
return CP_ACCESS_OK;
}
if (!(arm_hcr_el2_eff(env) & HCR_E2H)) {
return CP_ACCESS_TRAP;
}
return CP_ACCESS_OK;
}
/* Test if system register redirection is to occur in the current state. */
static bool redirect_for_e2h(CPUARMState *env)
{

6
target/arm/hvf/hvf.c
View File

@ -28,6 +28,8 @@
#include "arm-powerctl.h"
#include "target/arm/cpu.h"
#include "target/arm/internals.h"
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
#include "trace/trace-target_arm_hvf.h"
#include "migration/vmstate.h"
@ -1016,7 +1018,7 @@ static void hvf_raise_exception(CPUState *cpu, uint32_t excp,
static void hvf_psci_cpu_off(ARMCPU *arm_cpu)
{
int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity);
int32_t ret = arm_set_cpu_off(arm_cpu_mp_affinity(arm_cpu));
assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
}
@ -1045,7 +1047,7 @@ static bool hvf_handle_psci_call(CPUState *cpu)
int32_t ret = 0;
trace_hvf_psci_call(param[0], param[1], param[2], param[3],
arm_cpu->mp_affinity);
arm_cpu_mp_affinity(arm_cpu));
switch (param[0]) {
case QEMU_PSCI_0_2_FN_PSCI_VERSION:

1
target/arm/kvm.c
View File

@ -38,6 +38,7 @@
#include "qemu/log.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/ghes.h"
#include "target/arm/gtimer.h"
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO

1
target/arm/machine.c
View File

@ -7,6 +7,7 @@
#include "internals.h"
#include "cpu-features.h"
#include "migration/cpu.h"
#include "target/arm/gtimer.h"
static bool vfp_needed(void *opaque)
{

16
target/arm/multiprocessing.h Normal file
View File

@ -0,0 +1,16 @@
/*
* ARM multiprocessor CPU helpers
*
* Copyright (c) 2003 Fabrice Bellard
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
#ifndef TARGET_ARM_MULTIPROCESSING_H
#define TARGET_ARM_MULTIPROCESSING_H
#include "target/arm/cpu-qom.h"
uint64_t arm_cpu_mp_affinity(ARMCPU *cpu);
#endif

3
target/arm/tcg/psci.c
View File

@ -24,6 +24,7 @@
#include "sysemu/runstate.h"
#include "internals.h"
#include "arm-powerctl.h"
#include "target/arm/multiprocessing.h"
bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
{
@ -215,7 +216,7 @@ err:
return;
cpu_off:
ret = arm_set_cpu_off(cpu->mp_affinity);
ret = arm_set_cpu_off(arm_cpu_mp_affinity(cpu));
/* notreached */
/* sanity check in case something failed */
assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);

2
target/arm/tcg/tlb_helper.c
View File

@ -184,7 +184,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr,
* (and indeed syndrome does not have the EC field in it,
* because we masked that out in disas_set_insn_syndrome())
*/
bool is_vncr = (mmu_idx != MMU_INST_FETCH) &&
bool is_vncr = (access_type != MMU_INST_FETCH) &&
(env->exception.syndrome & ARM_EL_VNCR);
if (is_vncr) {

2
target/arm/tcg/translate-a64.c
View File

@ -8343,7 +8343,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
narrowfn(tcg_rd_narrowed, tcg_env, tcg_rd);
tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
if (i == 0) {
tcg_gen_mov_i64(tcg_final, tcg_rd);
tcg_gen_extract_i64(tcg_final, tcg_rd, 0, esize);
} else {
tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
}

47
target/xtensa/mmu_helper.c
View File

@ -224,22 +224,31 @@ static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v,
* Split TLB address into TLB way, entry index and VPN (with index).
* See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
*/
static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t *wi, uint32_t *ei)
static bool split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t *wi, uint32_t *ei)
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
*wi = v & (dtlb ? 0xf : 0x7);
split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) {
split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
return true;
} else {
return false;
}
} else {
*vpn = v & REGION_PAGE_MASK;
*wi = 0;
*ei = (v >> 29) & 0x7;
return true;
}
}
static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei)
{
const xtensa_tlb *tlb = dtlb ? &env->config->dtlb : &env->config->itlb;
assert(wi < tlb->nways && ei < tlb->way_size[wi]);
return dtlb ?
env->dtlb[wi] + ei :
env->itlb[wi] + ei;
@ -252,11 +261,14 @@ static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
uint32_t wi;
uint32_t ei;
split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
if (pwi) {
*pwi = wi;
if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
if (pwi) {
*pwi = wi;
}
return xtensa_tlb_get_entry(env, dtlb, wi, ei);
} else {
return NULL;
}
return xtensa_tlb_get_entry(env, dtlb, wi, ei);
}
static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
@ -482,7 +494,12 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
if (entry) {
return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
} else {
return 0;
}
} else {
return v & REGION_PAGE_MASK;
}
@ -491,7 +508,12 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
{
const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
return entry->paddr | entry->attr;
if (entry) {
return entry->paddr | entry->attr;
} else {
return 0;
}
}
void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
@ -499,7 +521,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
if (entry->variable && entry->asid) {
if (entry && entry->variable && entry->asid) {
tlb_flush_page(env_cpu(env), entry->vaddr);
entry->asid = 0;
}
@ -537,8 +559,9 @@ void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
uint32_t vpn;
uint32_t wi;
uint32_t ei;
split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) {
xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
}
}
/*!