mirror of https://gitlab.com/qemu-project/qemu
hw/intc: Remove omap2-intc device
Remove the OMAP2 specific code from omap_intc.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240903160751.4100218-41-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
aeaf7bb5aa
commit
7955b50ba1
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@ -50,8 +50,6 @@ struct OMAPIntcState {
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int level_only;
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uint32_t size;
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uint8_t revision;
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/* state */
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uint32_t new_agr[2];
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int sir_intr[2];
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@ -133,26 +131,6 @@ static void omap_set_intr(void *opaque, int irq, int req)
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}
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}
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/* Simplified version with no edge detection */
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static void omap_set_intr_noedge(void *opaque, int irq, int req)
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{
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OMAPIntcState *ih = opaque;
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uint32_t rise;
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struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
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int n = irq & 31;
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if (req) {
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rise = ~bank->inputs & (1 << n);
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if (rise) {
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bank->irqs |= bank->inputs |= rise;
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omap_inth_update(ih, 0);
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omap_inth_update(ih, 1);
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}
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} else
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bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
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}
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static uint64_t omap_inth_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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@ -420,259 +398,6 @@ static const TypeInfo omap_intc_info = {
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.class_init = omap_intc_class_init,
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};
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static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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OMAPIntcState *s = opaque;
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int offset = addr;
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int bank_no, line_no;
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struct omap_intr_handler_bank_s *bank = NULL;
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if ((offset & 0xf80) == 0x80) {
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bank_no = (offset & 0x60) >> 5;
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if (bank_no < s->nbanks) {
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offset &= ~0x60;
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bank = &s->bank[bank_no];
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} else {
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OMAP_BAD_REG(addr);
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return 0;
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}
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}
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switch (offset) {
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case 0x00: /* INTC_REVISION */
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return s->revision;
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case 0x10: /* INTC_SYSCONFIG */
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return (s->autoidle >> 2) & 1;
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case 0x14: /* INTC_SYSSTATUS */
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return 1; /* RESETDONE */
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case 0x40: /* INTC_SIR_IRQ */
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return s->sir_intr[0];
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case 0x44: /* INTC_SIR_FIQ */
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return s->sir_intr[1];
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case 0x48: /* INTC_CONTROL */
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return (!s->mask) << 2; /* GLOBALMASK */
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case 0x4c: /* INTC_PROTECTION */
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return 0;
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case 0x50: /* INTC_IDLE */
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return s->autoidle & 3;
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/* Per-bank registers */
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case 0x80: /* INTC_ITR */
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return bank->inputs;
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case 0x84: /* INTC_MIR */
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return bank->mask;
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case 0x88: /* INTC_MIR_CLEAR */
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case 0x8c: /* INTC_MIR_SET */
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return 0;
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case 0x90: /* INTC_ISR_SET */
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return bank->swi;
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case 0x94: /* INTC_ISR_CLEAR */
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return 0;
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case 0x98: /* INTC_PENDING_IRQ */
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return bank->irqs & ~bank->mask & ~bank->fiq;
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case 0x9c: /* INTC_PENDING_FIQ */
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return bank->irqs & ~bank->mask & bank->fiq;
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/* Per-line registers */
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case 0x100 ... 0x300: /* INTC_ILR */
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bank_no = (offset - 0x100) >> 7;
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if (bank_no > s->nbanks)
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break;
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bank = &s->bank[bank_no];
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line_no = (offset & 0x7f) >> 2;
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return (bank->priority[line_no] << 2) |
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((bank->fiq >> line_no) & 1);
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}
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OMAP_BAD_REG(addr);
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return 0;
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}
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static void omap2_inth_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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OMAPIntcState *s = opaque;
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int offset = addr;
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int bank_no, line_no;
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struct omap_intr_handler_bank_s *bank = NULL;
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if ((offset & 0xf80) == 0x80) {
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bank_no = (offset & 0x60) >> 5;
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if (bank_no < s->nbanks) {
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offset &= ~0x60;
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bank = &s->bank[bank_no];
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} else {
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OMAP_BAD_REG(addr);
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return;
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}
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}
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switch (offset) {
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case 0x10: /* INTC_SYSCONFIG */
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s->autoidle &= 4;
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s->autoidle |= (value & 1) << 2;
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if (value & 2) { /* SOFTRESET */
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omap_inth_reset(DEVICE(s));
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}
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return;
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case 0x48: /* INTC_CONTROL */
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s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */
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if (value & 2) { /* NEWFIQAGR */
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qemu_set_irq(s->parent_intr[1], 0);
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s->new_agr[1] = ~0;
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omap_inth_update(s, 1);
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}
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if (value & 1) { /* NEWIRQAGR */
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qemu_set_irq(s->parent_intr[0], 0);
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s->new_agr[0] = ~0;
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omap_inth_update(s, 0);
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}
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return;
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case 0x4c: /* INTC_PROTECTION */
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/* TODO: Make a bitmap (or sizeof(char)map) of access privileges
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* for every register, see Chapter 3 and 4 for privileged mode. */
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if (value & 1)
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fprintf(stderr, "%s: protection mode enable attempt\n",
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__func__);
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return;
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case 0x50: /* INTC_IDLE */
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s->autoidle &= ~3;
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s->autoidle |= value & 3;
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return;
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/* Per-bank registers */
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case 0x84: /* INTC_MIR */
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bank->mask = value;
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omap_inth_update(s, 0);
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omap_inth_update(s, 1);
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return;
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case 0x88: /* INTC_MIR_CLEAR */
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bank->mask &= ~value;
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omap_inth_update(s, 0);
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omap_inth_update(s, 1);
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return;
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case 0x8c: /* INTC_MIR_SET */
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bank->mask |= value;
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return;
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case 0x90: /* INTC_ISR_SET */
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bank->irqs |= bank->swi |= value;
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omap_inth_update(s, 0);
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omap_inth_update(s, 1);
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return;
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case 0x94: /* INTC_ISR_CLEAR */
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bank->swi &= ~value;
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bank->irqs = bank->swi & bank->inputs;
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return;
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/* Per-line registers */
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case 0x100 ... 0x300: /* INTC_ILR */
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bank_no = (offset - 0x100) >> 7;
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if (bank_no > s->nbanks)
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break;
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bank = &s->bank[bank_no];
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line_no = (offset & 0x7f) >> 2;
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bank->priority[line_no] = (value >> 2) & 0x3f;
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bank->fiq &= ~(1 << line_no);
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bank->fiq |= (value & 1) << line_no;
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return;
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case 0x00: /* INTC_REVISION */
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case 0x14: /* INTC_SYSSTATUS */
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case 0x40: /* INTC_SIR_IRQ */
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case 0x44: /* INTC_SIR_FIQ */
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case 0x80: /* INTC_ITR */
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case 0x98: /* INTC_PENDING_IRQ */
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case 0x9c: /* INTC_PENDING_FIQ */
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OMAP_RO_REG(addr);
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return;
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}
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OMAP_BAD_REG(addr);
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}
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static const MemoryRegionOps omap2_inth_mem_ops = {
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.read = omap2_inth_read,
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.write = omap2_inth_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void omap2_intc_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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OMAPIntcState *s = OMAP_INTC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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s->level_only = 1;
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s->nbanks = 3;
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sysbus_init_irq(sbd, &s->parent_intr[0]);
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sysbus_init_irq(sbd, &s->parent_intr[1]);
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qdev_init_gpio_in(dev, omap_set_intr_noedge, s->nbanks * 32);
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memory_region_init_io(&s->mmio, obj, &omap2_inth_mem_ops, s,
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"omap2-intc", 0x1000);
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sysbus_init_mmio(sbd, &s->mmio);
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}
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static void omap2_intc_realize(DeviceState *dev, Error **errp)
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{
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OMAPIntcState *s = OMAP_INTC(dev);
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if (!s->iclk) {
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error_setg(errp, "omap2-intc: iclk not connected");
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return;
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}
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if (!s->fclk) {
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error_setg(errp, "omap2-intc: fclk not connected");
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return;
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}
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}
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static Property omap2_intc_properties[] = {
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DEFINE_PROP_UINT8("revision", OMAPIntcState,
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revision, 0x21),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void omap2_intc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_legacy_reset(dc, omap_inth_reset);
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device_class_set_props(dc, omap2_intc_properties);
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/* Reason: pointer property "iclk", "fclk" */
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dc->user_creatable = false;
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dc->realize = omap2_intc_realize;
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}
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static const TypeInfo omap2_intc_info = {
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.name = "omap2-intc",
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.parent = TYPE_OMAP_INTC,
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.instance_init = omap2_intc_init,
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.class_init = omap2_intc_class_init,
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};
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static const TypeInfo omap_intc_type_info = {
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.name = TYPE_OMAP_INTC,
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.parent = TYPE_SYS_BUS_DEVICE,
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@ -684,7 +409,6 @@ static void omap_intc_register_types(void)
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{
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type_register_static(&omap_intc_type_info);
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type_register_static(&omap_intc_info);
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type_register_static(&omap2_intc_info);
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}
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type_init(omap_intc_register_types)
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