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tcg/i386: Implement vector TST{EQ,NE} for avx512

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-09-07 21:39:03 -07:00
parent d589674902
commit 782cffa4ce
2 changed files with 29 additions and 4 deletions
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31
tcg/i386/tcg-target.c.inc
View File

@ -462,6 +462,14 @@ static bool tcg_target_const_match(int64_t val, int ct,
#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16) #define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16)
#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW) #define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
#define OPC_VPTERNLOGQ (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX) #define OPC_VPTERNLOGQ (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPTESTMB (0x26 | P_EXT38 | P_DATA16 | P_EVEX)
#define OPC_VPTESTMW (0x26 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPTESTMD (0x27 | P_EXT38 | P_DATA16 | P_EVEX)
#define OPC_VPTESTMQ (0x27 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPTESTNMB (0x26 | P_EXT38 | P_SIMDF3 | P_EVEX)
#define OPC_VPTESTNMW (0x26 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX)
#define OPC_VPTESTNMD (0x27 | P_EXT38 | P_SIMDF3 | P_EVEX)
#define OPC_VPTESTNMQ (0x27 | P_EXT38 | P_SIMDF3 | P_VEXW | P_EVEX)
#define OPC_VZEROUPPER (0x77 | P_EXT) #define OPC_VZEROUPPER (0x77 | P_EXT)
#define OPC_XCHG_ax_r32 (0x90) #define OPC_XCHG_ax_r32 (0x90)
#define OPC_XCHG_EvGv (0x87) #define OPC_XCHG_EvGv (0x87)
@ -3145,6 +3153,13 @@ static void tcg_out_cmp_vec_k1(TCGContext *s, TCGType type, unsigned vece,
{ OPC_VPCMPB, OPC_VPCMPW, OPC_VPCMPD, OPC_VPCMPQ }, { OPC_VPCMPB, OPC_VPCMPW, OPC_VPCMPD, OPC_VPCMPQ },
{ OPC_VPCMPUB, OPC_VPCMPUW, OPC_VPCMPUD, OPC_VPCMPUQ } { OPC_VPCMPUB, OPC_VPCMPUW, OPC_VPCMPUD, OPC_VPCMPUQ }
}; };
static const int testm_insn[4] = {
OPC_VPTESTMB, OPC_VPTESTMW, OPC_VPTESTMD, OPC_VPTESTMQ
};
static const int testnm_insn[4] = {
OPC_VPTESTNMB, OPC_VPTESTNMW, OPC_VPTESTNMD, OPC_VPTESTNMQ
};
static const int cond_ext[16] = { static const int cond_ext[16] = {
[TCG_COND_EQ] = 0, [TCG_COND_EQ] = 0,
[TCG_COND_NE] = 4, [TCG_COND_NE] = 4,
@ -3160,9 +3175,19 @@ static void tcg_out_cmp_vec_k1(TCGContext *s, TCGType type, unsigned vece,
[TCG_COND_ALWAYS] = 7, [TCG_COND_ALWAYS] = 7,
}; };
tcg_out_vex_modrm_type(s, cmpm_insn[is_unsigned_cond(cond)][vece], switch (cond) {
/* k1 */ 1, v1, v2, type); case TCG_COND_TSTNE:
tcg_out8(s, cond_ext[cond]); tcg_out_vex_modrm_type(s, testm_insn[vece], /* k1 */ 1, v1, v2, type);
break;
case TCG_COND_TSTEQ:
tcg_out_vex_modrm_type(s, testnm_insn[vece], /* k1 */ 1, v1, v2, type);
break;
default:
tcg_out_vex_modrm_type(s, cmpm_insn[is_unsigned_cond(cond)][vece],
/* k1 */ 1, v1, v2, type);
tcg_out8(s, cond_ext[cond]);
break;
}
} }
static void tcg_out_k1_to_vec(TCGContext *s, TCGType type, static void tcg_out_k1_to_vec(TCGContext *s, TCGType type,

2
tcg/i386/tcg-target.h
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@ -224,7 +224,7 @@ typedef enum {
#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec have_avx512vl #define TCG_TARGET_HAS_bitsel_vec have_avx512vl
#define TCG_TARGET_HAS_cmpsel_vec 1 #define TCG_TARGET_HAS_cmpsel_vec 1
#define TCG_TARGET_HAS_tst_vec 0 #define TCG_TARGET_HAS_tst_vec have_avx512bw
#define TCG_TARGET_deposit_i32_valid(ofs, len) \ #define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && ((len) == 8 || (len) == 16)) || \ (((ofs) == 0 && ((len) == 8 || (len) == 16)) || \