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hw/arm/exynos4210: Coalesce board_irqs and irq_table

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The exynos4210 code currently has two very similar arrays of IRQs:

 * board_irqs is a field of the Exynos4210Irq struct which is filled
   in by exynos4210_init_board_irqs() with the appropriate qemu_irqs
   for each IRQ the board/SoC can assert
 * irq_table is a set of qemu_irqs pointed to from the
   Exynos4210State struct.  It's allocated in exynos4210_init_irq,
   and the only behaviour these irqs have is that they pass on the
   level to the equivalent board_irqs[] irq

The extra indirection through irq_table is unnecessary, so coalesce
these into a single irq_table[] array as a direct field in
Exynos4210State which exynos4210_init_board_irqs() fills in.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-6-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-04-04 16:46:45 +01:00
parent c9d4940a9b
commit 771dee52c0
3 changed files with 11 additions and 35 deletions
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6
hw/arm/exynos4210.c
View File

@ -228,10 +228,6 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
} }
/*** IRQs ***/
s->irq_table = exynos4210_init_irq(&s->irqs);
/* IRQ Gate */ /* IRQ Gate */
for (i = 0; i < EXYNOS4210_NCPUS; i++) { for (i = 0; i < EXYNOS4210_NCPUS; i++) {
DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]); DeviceState *orgate = DEVICE(&s->cpu_irq_orgate[i]);
@ -296,7 +292,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp)
sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR);
/* Initialize board IRQs. */ /* Initialize board IRQs. */
exynos4210_init_board_irqs(&s->irqs); exynos4210_init_board_irqs(s);
/*** Memory ***/ /*** Memory ***/

32
hw/intc/exynos4210_gic.c
View File

@ -192,30 +192,14 @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] = {
#define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100
#define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000
static void exynos4210_irq_handler(void *opaque, int irq, int level)
{
Exynos4210Irq *s = (Exynos4210Irq *)opaque;
/* Bypass */
qemu_set_irq(s->board_irqs[irq], level);
}
/*
* Initialize exynos4210 IRQ subsystem stub.
*/
qemu_irq *exynos4210_init_irq(Exynos4210Irq *s)
{
return qemu_allocate_irqs(exynos4210_irq_handler, s,
EXYNOS4210_MAX_INT_COMBINER_IN_IRQ);
}
/* /*
* Initialize board IRQs. * Initialize board IRQs.
* These IRQs contain splitted Int/External Combiner and External Gic IRQs. * These IRQs contain splitted Int/External Combiner and External Gic IRQs.
*/ */
void exynos4210_init_board_irqs(Exynos4210Irq *s) void exynos4210_init_board_irqs(Exynos4210State *s)
{ {
uint32_t grp, bit, irq_id, n; uint32_t grp, bit, irq_id, n;
Exynos4210Irq *is = &s->irqs;
for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { for (n = 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) {
irq_id = 0; irq_id = 0;
@ -230,11 +214,11 @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
irq_id = EXT_GIC_ID_MCT_G1; irq_id = EXT_GIC_ID_MCT_G1;
} }
if (irq_id) { if (irq_id) {
s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
s->ext_gic_irq[irq_id-32]); is->ext_gic_irq[irq_id - 32]);
} else { } else {
s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
s->ext_combiner_irq[n]); is->ext_combiner_irq[n]);
} }
} }
for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) {
@ -245,8 +229,8 @@ void exynos4210_init_board_irqs(Exynos4210Irq *s)
EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit];
if (irq_id) { if (irq_id) {
s->board_irqs[n] = qemu_irq_split(s->int_combiner_irq[n], s->irq_table[n] = qemu_irq_split(is->int_combiner_irq[n],
s->ext_gic_irq[irq_id-32]); is->ext_gic_irq[irq_id - 32]);
} }
} }
} }

8
include/hw/arm/exynos4210.h
View File

@ -83,7 +83,6 @@ typedef struct Exynos4210Irq {
qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
} Exynos4210Irq; } Exynos4210Irq;
struct Exynos4210State { struct Exynos4210State {
@ -92,7 +91,7 @@ struct Exynos4210State {
/*< public >*/ /*< public >*/
ARMCPU *cpu[EXYNOS4210_NCPUS]; ARMCPU *cpu[EXYNOS4210_NCPUS];
Exynos4210Irq irqs; Exynos4210Irq irqs;
qemu_irq *irq_table; qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
MemoryRegion chipid_mem; MemoryRegion chipid_mem;
MemoryRegion iram_mem; MemoryRegion iram_mem;
@ -112,12 +111,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
void exynos4210_write_secondary(ARMCPU *cpu, void exynos4210_write_secondary(ARMCPU *cpu,
const struct arm_boot_info *info); const struct arm_boot_info *info);
/* Initialize exynos4210 IRQ subsystem stub */
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
/* Initialize board IRQs. /* Initialize board IRQs.
* These IRQs contain splitted Int/External Combiner and External Gic IRQs */ * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
void exynos4210_init_board_irqs(Exynos4210Irq *s); void exynos4210_init_board_irqs(Exynos4210State *s);
/* Get IRQ number from exynos4210 IRQ subsystem stub. /* Get IRQ number from exynos4210 IRQ subsystem stub.
* To identify IRQ source use internal combiner group and bit number * To identify IRQ source use internal combiner group and bit number