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tcg: Standardize on TCGReg as the enum for hard registers

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Most targets did not name the enum; tci used TCGRegister.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Richard Henderson 2011-11-09 08:03:33 +00:00 committed by Alexander Graf
parent ef81522bc1
commit 771142c2a7
10 changed files with 36 additions and 36 deletions
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4
tcg/arm/tcg-target.h
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@ -27,7 +27,7 @@
#undef TCG_TARGET_WORDS_BIGENDIAN #undef TCG_TARGET_WORDS_BIGENDIAN
#undef TCG_TARGET_STACK_GROWSUP #undef TCG_TARGET_STACK_GROWSUP
enum { typedef enum {
TCG_REG_R0 = 0, TCG_REG_R0 = 0,
TCG_REG_R1, TCG_REG_R1,
TCG_REG_R2, TCG_REG_R2,
@ -44,7 +44,7 @@ enum {
TCG_REG_R13, TCG_REG_R13,
TCG_REG_R14, TCG_REG_R14,
TCG_REG_PC, TCG_REG_PC,
}; } TCGReg;
#define TCG_TARGET_NB_REGS 16 #define TCG_TARGET_NB_REGS 16

4
tcg/hppa/tcg-target.h
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@ -32,7 +32,7 @@
#define TCG_TARGET_NB_REGS 32 #define TCG_TARGET_NB_REGS 32
enum { typedef enum {
TCG_REG_R0 = 0, TCG_REG_R0 = 0,
TCG_REG_R1, TCG_REG_R1,
TCG_REG_RP, TCG_REG_RP,
@ -65,7 +65,7 @@ enum {
TCG_REG_RET1, TCG_REG_RET1,
TCG_REG_SP, TCG_REG_SP,
TCG_REG_R31, TCG_REG_R31,
}; } TCGReg;
#define TCG_CT_CONST_0 0x0100 #define TCG_CT_CONST_0 0x0100
#define TCG_CT_CONST_S5 0x0200 #define TCG_CT_CONST_S5 0x0200

4
tcg/i386/tcg-target.h
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@ -36,7 +36,7 @@
# define TCG_TARGET_NB_REGS 8 # define TCG_TARGET_NB_REGS 8
#endif #endif
enum { typedef enum {
TCG_REG_EAX = 0, TCG_REG_EAX = 0,
TCG_REG_ECX, TCG_REG_ECX,
TCG_REG_EDX, TCG_REG_EDX,
@ -64,7 +64,7 @@ enum {
TCG_REG_RBP = TCG_REG_EBP, TCG_REG_RBP = TCG_REG_EBP,
TCG_REG_RSI = TCG_REG_ESI, TCG_REG_RSI = TCG_REG_ESI,
TCG_REG_RDI = TCG_REG_EDI, TCG_REG_RDI = TCG_REG_EDI,
}; } TCGReg;
#define TCG_CT_CONST_S32 0x100 #define TCG_CT_CONST_S32 0x100
#define TCG_CT_CONST_U32 0x200 #define TCG_CT_CONST_U32 0x200

4
tcg/ia64/tcg-target.h
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@ -26,7 +26,7 @@
/* We only map the first 64 registers */ /* We only map the first 64 registers */
#define TCG_TARGET_NB_REGS 64 #define TCG_TARGET_NB_REGS 64
enum { typedef enum {
TCG_REG_R0 = 0, TCG_REG_R0 = 0,
TCG_REG_R1, TCG_REG_R1,
TCG_REG_R2, TCG_REG_R2,
@ -91,7 +91,7 @@ enum {
TCG_REG_R61, TCG_REG_R61,
TCG_REG_R62, TCG_REG_R62,
TCG_REG_R63, TCG_REG_R63,
}; } TCGReg;
#define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_ZERO 0x100
#define TCG_CT_CONST_S22 0x200 #define TCG_CT_CONST_S22 0x200

4
tcg/mips/tcg-target.h
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@ -31,7 +31,7 @@
#define TCG_TARGET_NB_REGS 32 #define TCG_TARGET_NB_REGS 32
enum { typedef enum {
TCG_REG_ZERO = 0, TCG_REG_ZERO = 0,
TCG_REG_AT, TCG_REG_AT,
TCG_REG_V0, TCG_REG_V0,
@ -64,7 +64,7 @@ enum {
TCG_REG_SP, TCG_REG_SP,
TCG_REG_FP, TCG_REG_FP,
TCG_REG_RA, TCG_REG_RA,
}; } TCGReg;
#define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_ZERO 0x100
#define TCG_CT_CONST_U16 0x200 #define TCG_CT_CONST_U16 0x200

4
tcg/ppc/tcg-target.h
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@ -26,7 +26,7 @@
#define TCG_TARGET_WORDS_BIGENDIAN #define TCG_TARGET_WORDS_BIGENDIAN
#define TCG_TARGET_NB_REGS 32 #define TCG_TARGET_NB_REGS 32
enum { typedef enum {
TCG_REG_R0 = 0, TCG_REG_R0 = 0,
TCG_REG_R1, TCG_REG_R1,
TCG_REG_R2, TCG_REG_R2,
@ -59,7 +59,7 @@ enum {
TCG_REG_R29, TCG_REG_R29,
TCG_REG_R30, TCG_REG_R30,
TCG_REG_R31 TCG_REG_R31
}; } TCGReg;
/* used for function call generation */ /* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_R1 #define TCG_REG_CALL_STACK TCG_REG_R1

4
tcg/ppc64/tcg-target.h
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@ -26,7 +26,7 @@
#define TCG_TARGET_WORDS_BIGENDIAN #define TCG_TARGET_WORDS_BIGENDIAN
#define TCG_TARGET_NB_REGS 32 #define TCG_TARGET_NB_REGS 32
enum { typedef enum {
TCG_REG_R0 = 0, TCG_REG_R0 = 0,
TCG_REG_R1, TCG_REG_R1,
TCG_REG_R2, TCG_REG_R2,
@ -59,7 +59,7 @@ enum {
TCG_REG_R29, TCG_REG_R29,
TCG_REG_R30, TCG_REG_R30,
TCG_REG_R31 TCG_REG_R31
}; } TCGReg;
/* used for function call generation */ /* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_R1 #define TCG_REG_CALL_STACK TCG_REG_R1

4
tcg/sparc/tcg-target.h
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@ -27,7 +27,7 @@
#define TCG_TARGET_NB_REGS 32 #define TCG_TARGET_NB_REGS 32
enum { typedef enum {
TCG_REG_G0 = 0, TCG_REG_G0 = 0,
TCG_REG_G1, TCG_REG_G1,
TCG_REG_G2, TCG_REG_G2,
@ -60,7 +60,7 @@ enum {
TCG_REG_I5, TCG_REG_I5,
TCG_REG_I6, TCG_REG_I6,
TCG_REG_I7, TCG_REG_I7,
}; } TCGReg;
#define TCG_CT_CONST_S11 0x100 #define TCG_CT_CONST_S11 0x100
#define TCG_CT_CONST_S13 0x200 #define TCG_CT_CONST_S13 0x200

2
tcg/tci/tcg-target.h
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@ -150,7 +150,7 @@ typedef enum {
#endif #endif
/* Special value UINT8_MAX is used by TCI to encode constant values. */ /* Special value UINT8_MAX is used by TCI to encode constant values. */
TCG_CONST = UINT8_MAX TCG_CONST = UINT8_MAX
} TCGRegister; } TCGReg;
void tci_disas(uint8_t opc); void tci_disas(uint8_t opc);

38
tci.c
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@ -63,90 +63,90 @@ void *tci_tb_ptr;
static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS]; static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
static tcg_target_ulong tci_read_reg(TCGRegister index) static tcg_target_ulong tci_read_reg(TCGReg index)
{ {
assert(index < ARRAY_SIZE(tci_reg)); assert(index < ARRAY_SIZE(tci_reg));
return tci_reg[index]; return tci_reg[index];
} }
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
static int8_t tci_read_reg8s(TCGRegister index) static int8_t tci_read_reg8s(TCGReg index)
{ {
return (int8_t)tci_read_reg(index); return (int8_t)tci_read_reg(index);
} }
#endif #endif
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
static int16_t tci_read_reg16s(TCGRegister index) static int16_t tci_read_reg16s(TCGReg index)
{ {
return (int16_t)tci_read_reg(index); return (int16_t)tci_read_reg(index);
} }
#endif #endif
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
static int32_t tci_read_reg32s(TCGRegister index) static int32_t tci_read_reg32s(TCGReg index)
{ {
return (int32_t)tci_read_reg(index); return (int32_t)tci_read_reg(index);
} }
#endif #endif
static uint8_t tci_read_reg8(TCGRegister index) static uint8_t tci_read_reg8(TCGReg index)
{ {
return (uint8_t)tci_read_reg(index); return (uint8_t)tci_read_reg(index);
} }
static uint16_t tci_read_reg16(TCGRegister index) static uint16_t tci_read_reg16(TCGReg index)
{ {
return (uint16_t)tci_read_reg(index); return (uint16_t)tci_read_reg(index);
} }
static uint32_t tci_read_reg32(TCGRegister index) static uint32_t tci_read_reg32(TCGReg index)
{ {
return (uint32_t)tci_read_reg(index); return (uint32_t)tci_read_reg(index);
} }
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
static uint64_t tci_read_reg64(TCGRegister index) static uint64_t tci_read_reg64(TCGReg index)
{ {
return tci_read_reg(index); return tci_read_reg(index);
} }
#endif #endif
static void tci_write_reg(TCGRegister index, tcg_target_ulong value) static void tci_write_reg(TCGReg index, tcg_target_ulong value)
{ {
assert(index < ARRAY_SIZE(tci_reg)); assert(index < ARRAY_SIZE(tci_reg));
assert(index != TCG_AREG0); assert(index != TCG_AREG0);
tci_reg[index] = value; tci_reg[index] = value;
} }
static void tci_write_reg8s(TCGRegister index, int8_t value) static void tci_write_reg8s(TCGReg index, int8_t value)
{ {
tci_write_reg(index, value); tci_write_reg(index, value);
} }
static void tci_write_reg16s(TCGRegister index, int16_t value) static void tci_write_reg16s(TCGReg index, int16_t value)
{ {
tci_write_reg(index, value); tci_write_reg(index, value);
} }
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
static void tci_write_reg32s(TCGRegister index, int32_t value) static void tci_write_reg32s(TCGReg index, int32_t value)
{ {
tci_write_reg(index, value); tci_write_reg(index, value);
} }
#endif #endif
static void tci_write_reg8(TCGRegister index, uint8_t value) static void tci_write_reg8(TCGReg index, uint8_t value)
{ {
tci_write_reg(index, value); tci_write_reg(index, value);
} }
static void tci_write_reg16(TCGRegister index, uint16_t value) static void tci_write_reg16(TCGReg index, uint16_t value)
{ {
tci_write_reg(index, value); tci_write_reg(index, value);
} }
static void tci_write_reg32(TCGRegister index, uint32_t value) static void tci_write_reg32(TCGReg index, uint32_t value)
{ {
tci_write_reg(index, value); tci_write_reg(index, value);
} }
@ -159,7 +159,7 @@ static void tci_write_reg64(uint32_t high_index, uint32_t low_index,
tci_write_reg(high_index, value >> 32); tci_write_reg(high_index, value >> 32);
} }
#elif TCG_TARGET_REG_BITS == 64 #elif TCG_TARGET_REG_BITS == 64
static void tci_write_reg64(TCGRegister index, uint64_t value) static void tci_write_reg64(TCGReg index, uint64_t value)
{ {
tci_write_reg(index, value); tci_write_reg(index, value);
} }
@ -290,7 +290,7 @@ static target_ulong tci_read_ulong(uint8_t **tb_ptr)
static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr)
{ {
tcg_target_ulong value; tcg_target_ulong value;
TCGRegister r = **tb_ptr; TCGReg r = **tb_ptr;
*tb_ptr += 1; *tb_ptr += 1;
if (r == TCG_CONST) { if (r == TCG_CONST) {
value = tci_read_i(tb_ptr); value = tci_read_i(tb_ptr);
@ -304,7 +304,7 @@ static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr)
static uint32_t tci_read_ri32(uint8_t **tb_ptr) static uint32_t tci_read_ri32(uint8_t **tb_ptr)
{ {
uint32_t value; uint32_t value;
TCGRegister r = **tb_ptr; TCGReg r = **tb_ptr;
*tb_ptr += 1; *tb_ptr += 1;
if (r == TCG_CONST) { if (r == TCG_CONST) {
value = tci_read_i32(tb_ptr); value = tci_read_i32(tb_ptr);
@ -326,7 +326,7 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr)
static uint64_t tci_read_ri64(uint8_t **tb_ptr) static uint64_t tci_read_ri64(uint8_t **tb_ptr)
{ {
uint64_t value; uint64_t value;
TCGRegister r = **tb_ptr; TCGReg r = **tb_ptr;
*tb_ptr += 1; *tb_ptr += 1;
if (r == TCG_CONST) { if (r == TCG_CONST) {
value = tci_read_i64(tb_ptr); value = tci_read_i64(tb_ptr);