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Hexagon updates: lldb preds, v66 CPU, F2_conv* fix

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Merge tag 'pull-hex-20240807' of https://github.com/quic/qemu into staging

Hexagon updates: lldb preds, v66 CPU, F2_conv* fix

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# gpg: Signature made Thu 08 Aug 2024 01:39:52 PM AEST
# gpg:                using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# gpg:                 aka "Brian Cain <bcain@kernel.org>" [unknown]
# gpg:                 aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown]
# gpg:                 aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown]
# gpg:                 aka "bcain" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF  49E0 175C 464E 541B 6D47
#      Subkey fingerprint: 3D66 AAE4 7459 4824 C88C  E0F8 1A54 AFB8 E564 6C32

* tag 'pull-hex-20240807' of https://github.com/quic/qemu:
  target/hexagon: switch to dc set_props() list
  target/hexagon: define a v66 CPU
  MAINTAINERS: Add my hexagon git tree
  target/hexagon/idef-parser: Remove self-assignment
  Hexagon: lldb read/write predicate registers p0/p1/p2/p3
  Hexagon: fix F2_conv_* instructions for negative zero

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-08-08 16:08:18 +10:00
commit 75c7f57403
8 changed files with 55 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -245,6 +245,7 @@ F: disas/hexagon.c
F: configs/targets/hexagon-linux-user/default.mak F: configs/targets/hexagon-linux-user/default.mak
F: docker/dockerfiles/debian-hexagon-cross.docker F: docker/dockerfiles/debian-hexagon-cross.docker
F: gdb-xml/hexagon*.xml F: gdb-xml/hexagon*.xml
T: git https://github.com/quic/qemu.git hex-next
Hexagon idef-parser Hexagon idef-parser
M: Alessandro Di Federico <ale@rev.ng> M: Alessandro Di Federico <ale@rev.ng>

6
gdb-xml/hexagon-core.xml
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@ -1,6 +1,6 @@
<?xml version="1.0"?> <?xml version="1.0"?>
<!-- <!--
Copyright(c) 2023 Qualcomm Innovation Center, Inc. All Rights Reserved. Copyright(c) 2023-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
This work is licensed under the terms of the GNU GPL, version 2 or This work is licensed under the terms of the GNU GPL, version 2 or
(at your option) any later version. See the COPYING file in the (at your option) any later version. See the COPYING file in the
@ -80,5 +80,9 @@
<reg name="c29" bitsize="32" offset="244" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="61"/> <reg name="c29" bitsize="32" offset="244" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="61"/>
<reg name="utimerlo" bitsize="32" offset="248" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="62"/> <reg name="utimerlo" bitsize="32" offset="248" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="62"/>
<reg name="utimerhi" bitsize="32" offset="252" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="63"/> <reg name="utimerhi" bitsize="32" offset="252" encoding="uint" format="hex" group="Thread Registers" dwarf_regnum="63"/>
<reg name="p0" bitsize="8" offset="256" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="64"/>
<reg name="p1" bitsize="8" offset="257" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="65"/>
<reg name="p2" bitsize="8" offset="258" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="66"/>
<reg name="p3" bitsize="8" offset="259" encoding="uint" format="hex" group="Predicate Registers" dwarf_regnum="67"/>
</feature> </feature>

1
target/hexagon/cpu-qom.h
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@ -16,6 +16,7 @@
#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU #define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU
#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX)
#define TYPE_HEXAGON_CPU_V66 HEXAGON_CPU_TYPE_NAME("v66")
#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67")
#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") #define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68")
#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") #define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69")

20
target/hexagon/cpu.c
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@ -26,6 +26,7 @@
#include "tcg/tcg.h" #include "tcg/tcg.h"
#include "exec/gdbstub.h" #include "exec/gdbstub.h"
static void hexagon_v66_cpu_init(Object *obj) { }
static void hexagon_v67_cpu_init(Object *obj) { } static void hexagon_v67_cpu_init(Object *obj) { }
static void hexagon_v68_cpu_init(Object *obj) { } static void hexagon_v68_cpu_init(Object *obj) { }
static void hexagon_v69_cpu_init(Object *obj) { } static void hexagon_v69_cpu_init(Object *obj) { }
@ -47,13 +48,13 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)
return oc; return oc;
} }
static Property hexagon_lldb_compat_property = static Property hexagon_cpu_properties[] = {
DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false); DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false),
static Property hexagon_lldb_stack_adjust_property = DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 0,
DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, qdev_prop_uint32, target_ulong),
0, qdev_prop_uint32, target_ulong); DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true),
static Property hexagon_short_circuit_property = DEFINE_PROP_END_OF_LIST()
DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true); };
const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = { const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
@ -316,9 +317,6 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)
static void hexagon_cpu_init(Object *obj) static void hexagon_cpu_init(Object *obj)
{ {
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property);
qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_property);
qdev_property_add_static(DEVICE(obj), &hexagon_short_circuit_property);
} }
#include "hw/core/tcg-cpu-ops.h" #include "hw/core/tcg-cpu-ops.h"
@ -339,6 +337,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
device_class_set_parent_realize(dc, hexagon_cpu_realize, device_class_set_parent_realize(dc, hexagon_cpu_realize,
&mcc->parent_realize); &mcc->parent_realize);
device_class_set_props(dc, hexagon_cpu_properties);
resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL, resettable_class_set_parent_phases(rc, NULL, hexagon_cpu_reset_hold, NULL,
&mcc->parent_phases); &mcc->parent_phases);
@ -373,6 +372,7 @@ static const TypeInfo hexagon_cpu_type_infos[] = {
.class_size = sizeof(HexagonCPUClass), .class_size = sizeof(HexagonCPUClass),
.class_init = hexagon_cpu_class_init, .class_init = hexagon_cpu_class_init,
}, },
DEFINE_CPU(TYPE_HEXAGON_CPU_V66, hexagon_v66_cpu_init),
DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init), DEFINE_CPU(TYPE_HEXAGON_CPU_V67, hexagon_v67_cpu_init),
DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init), DEFINE_CPU(TYPE_HEXAGON_CPU_V68, hexagon_v68_cpu_init),
DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init), DEFINE_CPU(TYPE_HEXAGON_CPU_V69, hexagon_v69_cpu_init),

19
target/hexagon/gdbstub.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved. * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -36,6 +36,14 @@ int hexagon_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return gdb_get_regl(mem_buf, env->gpr[n]); return gdb_get_regl(mem_buf, env->gpr[n]);
} }
n -= TOTAL_PER_THREAD_REGS;
if (n < NUM_PREGS) {
return gdb_get_reg8(mem_buf, env->pred[n]);
}
n -= NUM_PREGS;
g_assert_not_reached(); g_assert_not_reached();
} }
@ -56,6 +64,15 @@ int hexagon_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
return sizeof(target_ulong); return sizeof(target_ulong);
} }
n -= TOTAL_PER_THREAD_REGS;
if (n < NUM_PREGS) {
env->pred[n] = ldtul_p(mem_buf) & 0xff;
return sizeof(uint8_t);
}
n -= NUM_PREGS;
g_assert_not_reached(); g_assert_not_reached();
} }

1
target/hexagon/idef-parser/idef-parser.y
View File

@ -800,7 +800,6 @@ rvalue : FAIL
lvalue : FAIL lvalue : FAIL
{ {
@1.last_column = @1.last_column;
yyassert(c, &@1, false, "Encountered a FAIL token as lvalue.\n"); yyassert(c, &@1, false, "Encountered a FAIL token as lvalue.\n");
} }
| REG | REG

18
target/hexagon/op_helper.c
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@ -1,5 +1,5 @@
/* /*
* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -683,7 +683,7 @@ uint32_t HELPER(conv_sf2uw)(CPUHexagonState *env, float32 RsV)
uint32_t RdV; uint32_t RdV;
arch_fpop_start(env); arch_fpop_start(env);
/* Hexagon checks the sign before rounding */ /* Hexagon checks the sign before rounding */
if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) { if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) {
float_raise(float_flag_invalid, &env->fp_status); float_raise(float_flag_invalid, &env->fp_status);
RdV = 0; RdV = 0;
} else { } else {
@ -713,7 +713,7 @@ uint64_t HELPER(conv_sf2ud)(CPUHexagonState *env, float32 RsV)
uint64_t RddV; uint64_t RddV;
arch_fpop_start(env); arch_fpop_start(env);
/* Hexagon checks the sign before rounding */ /* Hexagon checks the sign before rounding */
if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) { if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) {
float_raise(float_flag_invalid, &env->fp_status); float_raise(float_flag_invalid, &env->fp_status);
RddV = 0; RddV = 0;
} else { } else {
@ -743,7 +743,7 @@ uint32_t HELPER(conv_df2uw)(CPUHexagonState *env, float64 RssV)
uint32_t RdV; uint32_t RdV;
arch_fpop_start(env); arch_fpop_start(env);
/* Hexagon checks the sign before rounding */ /* Hexagon checks the sign before rounding */
if (float64_is_neg(RssV) && !float64_is_any_nan(RssV)) { if (float64_is_neg(RssV) && !float64_is_any_nan(RssV) && !float64_is_zero(RssV)) {
float_raise(float_flag_invalid, &env->fp_status); float_raise(float_flag_invalid, &env->fp_status);
RdV = 0; RdV = 0;
} else { } else {
@ -773,7 +773,7 @@ uint64_t HELPER(conv_df2ud)(CPUHexagonState *env, float64 RssV)
uint64_t RddV; uint64_t RddV;
arch_fpop_start(env); arch_fpop_start(env);
/* Hexagon checks the sign before rounding */ /* Hexagon checks the sign before rounding */
if (float64_is_neg(RssV) && !float64_is_any_nan(RssV)) { if (float64_is_neg(RssV) && !float64_is_any_nan(RssV) && !float64_is_zero(RssV)) {
float_raise(float_flag_invalid, &env->fp_status); float_raise(float_flag_invalid, &env->fp_status);
RddV = 0; RddV = 0;
} else { } else {
@ -803,7 +803,7 @@ uint32_t HELPER(conv_sf2uw_chop)(CPUHexagonState *env, float32 RsV)
uint32_t RdV; uint32_t RdV;
arch_fpop_start(env); arch_fpop_start(env);
/* Hexagon checks the sign before rounding */ /* Hexagon checks the sign before rounding */
if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) { if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) {
float_raise(float_flag_invalid, &env->fp_status); float_raise(float_flag_invalid, &env->fp_status);
RdV = 0; RdV = 0;
} else { } else {
@ -833,7 +833,7 @@ uint64_t HELPER(conv_sf2ud_chop)(CPUHexagonState *env, float32 RsV)
uint64_t RddV; uint64_t RddV;
arch_fpop_start(env); arch_fpop_start(env);
/* Hexagon checks the sign before rounding */ /* Hexagon checks the sign before rounding */
if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) { if (float32_is_neg(RsV) && !float32_is_any_nan(RsV) && !float32_is_zero(RsV)) {
float_raise(float_flag_invalid, &env->fp_status); float_raise(float_flag_invalid, &env->fp_status);
RddV = 0; RddV = 0;
} else { } else {
@ -863,7 +863,7 @@ uint32_t HELPER(conv_df2uw_chop)(CPUHexagonState *env, float64 RssV)
uint32_t RdV; uint32_t RdV;
arch_fpop_start(env); arch_fpop_start(env);
/* Hexagon checks the sign before rounding */ /* Hexagon checks the sign before rounding */
if (float64_is_neg(RssV) && !float64_is_any_nan(RssV)) { if (float64_is_neg(RssV) && !float64_is_any_nan(RssV) && !float64_is_zero(RssV)) {
float_raise(float_flag_invalid, &env->fp_status); float_raise(float_flag_invalid, &env->fp_status);
RdV = 0; RdV = 0;
} else { } else {
@ -893,7 +893,7 @@ uint64_t HELPER(conv_df2ud_chop)(CPUHexagonState *env, float64 RssV)
uint64_t RddV; uint64_t RddV;
arch_fpop_start(env); arch_fpop_start(env);
/* Hexagon checks the sign before rounding */ /* Hexagon checks the sign before rounding */
if (float64_is_neg(RssV) && !float64_is_any_nan(RssV)) { if (float64_is_neg(RssV) && !float64_is_any_nan(RssV) && !float64_is_zero(RssV)) {
float_raise(float_flag_invalid, &env->fp_status); float_raise(float_flag_invalid, &env->fp_status);
RddV = 0; RddV = 0;
} else { } else {

12
tests/tcg/hexagon/usr.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright(c) 2022-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. * Copyright(c) 2022-2024 Qualcomm Innovation Center, Inc. All Rights Reserved.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -1007,6 +1007,11 @@ int main()
TEST_P_OP_R(conv_sf2d_chop, SF_QNaN, 0xffffffffffffffffULL, USR_FPINVF); TEST_P_OP_R(conv_sf2d_chop, SF_QNaN, 0xffffffffffffffffULL, USR_FPINVF);
TEST_P_OP_R(conv_sf2d_chop, SF_SNaN, 0xffffffffffffffffULL, USR_FPINVF); TEST_P_OP_R(conv_sf2d_chop, SF_SNaN, 0xffffffffffffffffULL, USR_FPINVF);
TEST_R_OP_R(conv_sf2uw, SF_zero_neg, 0, USR_CLEAR);
TEST_R_OP_R(conv_sf2uw_chop, SF_zero_neg, 0, USR_CLEAR);
TEST_P_OP_R(conv_sf2ud, SF_zero_neg, 0, USR_CLEAR);
TEST_P_OP_R(conv_sf2ud_chop, SF_zero_neg, 0, USR_CLEAR);
TEST_R_OP_P(conv_df2sf, DF_QNaN, SF_HEX_NaN, USR_CLEAR); TEST_R_OP_P(conv_df2sf, DF_QNaN, SF_HEX_NaN, USR_CLEAR);
TEST_R_OP_P(conv_df2sf, DF_SNaN, SF_HEX_NaN, USR_FPINVF); TEST_R_OP_P(conv_df2sf, DF_SNaN, SF_HEX_NaN, USR_FPINVF);
TEST_R_OP_P(conv_df2uw, DF_QNaN, 0xffffffff, USR_FPINVF); TEST_R_OP_P(conv_df2uw, DF_QNaN, 0xffffffff, USR_FPINVF);
@ -1020,6 +1025,11 @@ int main()
TEST_R_OP_P(conv_df2uw_chop, DF_QNaN, 0xffffffff, USR_FPINVF); TEST_R_OP_P(conv_df2uw_chop, DF_QNaN, 0xffffffff, USR_FPINVF);
TEST_R_OP_P(conv_df2uw_chop, DF_SNaN, 0xffffffff, USR_FPINVF); TEST_R_OP_P(conv_df2uw_chop, DF_SNaN, 0xffffffff, USR_FPINVF);
TEST_R_OP_P(conv_df2uw, DF_zero_neg, 0, USR_CLEAR);
TEST_R_OP_P(conv_df2uw_chop, DF_zero_neg, 0, USR_CLEAR);
TEST_P_OP_P(conv_df2ud, DF_zero_neg, 0, USR_CLEAR);
TEST_P_OP_P(conv_df2ud_chop, DF_zero_neg, 0, USR_CLEAR);
/* Test for typo in HELPER(conv_df2uw_chop) */ /* Test for typo in HELPER(conv_df2uw_chop) */
TEST_R_OP_P(conv_df2uw_chop, 0xffffff7f00000001ULL, 0xffffffff, USR_FPINVF); TEST_R_OP_P(conv_df2uw_chop, 0xffffff7f00000001ULL, 0xffffffff, USR_FPINVF);