target/arm: Implement SVE Integer Compare - Vectors Group
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180613015641.5667-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
d3fe4a29d7
commit
757f9cff1b
@ -490,6 +490,121 @@ DEF_HELPER_FLAGS_4(sve_rbit_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_splice, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpeq_ppzz_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpne_ppzz_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpge_ppzz_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpgt_ppzz_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphi_ppzz_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphs_ppzz_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpeq_ppzz_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpne_ppzz_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpge_ppzz_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpgt_ppzz_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphi_ppzz_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphs_ppzz_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpeq_ppzz_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpne_ppzz_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpge_ppzz_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpgt_ppzz_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphi_ppzz_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphs_ppzz_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpeq_ppzz_d, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpne_ppzz_d, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpge_ppzz_d, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpgt_ppzz_d, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphi_ppzz_d, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphs_ppzz_d, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpeq_ppzw_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpne_ppzw_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpge_ppzw_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpgt_ppzw_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphi_ppzw_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphs_ppzw_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmple_ppzw_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmplt_ppzw_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmplo_ppzw_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpls_ppzw_b, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpeq_ppzw_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpne_ppzw_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpge_ppzw_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpgt_ppzw_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphi_ppzw_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphs_ppzw_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmple_ppzw_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmplt_ppzw_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmplo_ppzw_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpls_ppzw_h, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpeq_ppzw_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpne_ppzw_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpge_ppzw_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpgt_ppzw_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphi_ppzw_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmphs_ppzw_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmple_ppzw_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmplt_ppzw_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmplo_ppzw_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_cmpls_ppzw_s, TCG_CALL_NO_RWG,
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i32, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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@ -99,6 +99,7 @@
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@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
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&rprr_esz rm=%reg_movprfx
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@rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
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@pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz
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# Three register operand, with governing predicate, vector element size
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@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
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@ -472,6 +473,29 @@ SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
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# SVE select vector elements (predicated)
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SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm
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### SVE Integer Compare - Vectors Group
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# SVE integer compare_vectors
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CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm
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CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm
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CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
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CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
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CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm
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CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm
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# SVE integer compare with wide elements
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# Note these require esz != 3.
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CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm
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CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm
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CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
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CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
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CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
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CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
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CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
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CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
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CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm
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CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
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### SVE Predicate Logical Operations Group
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# SVE predicate logical operations
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@ -74,6 +74,28 @@ static uint32_t iter_predtest_fwd(uint64_t d, uint64_t g, uint32_t flags)
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return flags;
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}
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/* This is an iterative function, called for each Pd and Pg word
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* moving backward.
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*/
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static uint32_t iter_predtest_bwd(uint64_t d, uint64_t g, uint32_t flags)
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{
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if (likely(g)) {
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/* Compute C from first (i.e last) !(D & G).
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Use bit 2 to signal first G bit seen. */
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if (!(flags & 4)) {
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flags += 4 - 1; /* add bit 2, subtract C from PREDTEST_INIT */
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flags |= (d & pow2floor(g)) == 0;
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}
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/* Accumulate Z from each D & G. */
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flags |= ((d & g) != 0) << 1;
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/* Compute N from last (i.e first) D & G. Replace previous. */
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flags = deposit32(flags, 31, 1, (d & (g & -g)) != 0);
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}
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return flags;
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}
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/* The same for a single word predicate. */
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uint32_t HELPER(sve_predtest1)(uint64_t d, uint64_t g)
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{
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@ -2201,3 +2223,168 @@ void HELPER(sve_sel_zpzz_d)(void *vd, void *vn, void *vm,
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d[i] = (pg[H1(i)] & 1 ? nn : mm);
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}
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}
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/* Two operand comparison controlled by a predicate.
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* ??? It is very tempting to want to be able to expand this inline
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* with x86 instructions, e.g.
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*
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* vcmpeqw zm, zn, %ymm0
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* vpmovmskb %ymm0, %eax
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* and $0x5555, %eax
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* and pg, %eax
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*
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* or even aarch64, e.g.
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*
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* // mask = 4000 1000 0400 0100 0040 0010 0004 0001
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* cmeq v0.8h, zn, zm
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* and v0.8h, v0.8h, mask
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* addv h0, v0.8h
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* and v0.8b, pg
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*
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* However, coming up with an abstraction that allows vector inputs and
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* a scalar output, and also handles the byte-ordering of sub-uint64_t
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* scalar outputs, is tricky.
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*/
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#define DO_CMP_PPZZ(NAME, TYPE, OP, H, MASK) \
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uint32_t HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \
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{ \
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intptr_t opr_sz = simd_oprsz(desc); \
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uint32_t flags = PREDTEST_INIT; \
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intptr_t i = opr_sz; \
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do { \
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uint64_t out = 0, pg; \
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do { \
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i -= sizeof(TYPE), out <<= sizeof(TYPE); \
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TYPE nn = *(TYPE *)(vn + H(i)); \
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TYPE mm = *(TYPE *)(vm + H(i)); \
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out |= nn OP mm; \
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} while (i & 63); \
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pg = *(uint64_t *)(vg + (i >> 3)) & MASK; \
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out &= pg; \
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*(uint64_t *)(vd + (i >> 3)) = out; \
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flags = iter_predtest_bwd(out, pg, flags); \
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} while (i > 0); \
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return flags; \
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}
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#define DO_CMP_PPZZ_B(NAME, TYPE, OP) \
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DO_CMP_PPZZ(NAME, TYPE, OP, H1, 0xffffffffffffffffull)
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#define DO_CMP_PPZZ_H(NAME, TYPE, OP) \
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DO_CMP_PPZZ(NAME, TYPE, OP, H1_2, 0x5555555555555555ull)
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#define DO_CMP_PPZZ_S(NAME, TYPE, OP) \
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DO_CMP_PPZZ(NAME, TYPE, OP, H1_4, 0x1111111111111111ull)
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#define DO_CMP_PPZZ_D(NAME, TYPE, OP) \
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DO_CMP_PPZZ(NAME, TYPE, OP, , 0x0101010101010101ull)
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DO_CMP_PPZZ_B(sve_cmpeq_ppzz_b, uint8_t, ==)
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DO_CMP_PPZZ_H(sve_cmpeq_ppzz_h, uint16_t, ==)
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DO_CMP_PPZZ_S(sve_cmpeq_ppzz_s, uint32_t, ==)
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DO_CMP_PPZZ_D(sve_cmpeq_ppzz_d, uint64_t, ==)
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DO_CMP_PPZZ_B(sve_cmpne_ppzz_b, uint8_t, !=)
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DO_CMP_PPZZ_H(sve_cmpne_ppzz_h, uint16_t, !=)
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DO_CMP_PPZZ_S(sve_cmpne_ppzz_s, uint32_t, !=)
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DO_CMP_PPZZ_D(sve_cmpne_ppzz_d, uint64_t, !=)
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DO_CMP_PPZZ_B(sve_cmpgt_ppzz_b, int8_t, >)
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DO_CMP_PPZZ_H(sve_cmpgt_ppzz_h, int16_t, >)
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DO_CMP_PPZZ_S(sve_cmpgt_ppzz_s, int32_t, >)
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DO_CMP_PPZZ_D(sve_cmpgt_ppzz_d, int64_t, >)
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DO_CMP_PPZZ_B(sve_cmpge_ppzz_b, int8_t, >=)
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DO_CMP_PPZZ_H(sve_cmpge_ppzz_h, int16_t, >=)
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DO_CMP_PPZZ_S(sve_cmpge_ppzz_s, int32_t, >=)
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DO_CMP_PPZZ_D(sve_cmpge_ppzz_d, int64_t, >=)
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DO_CMP_PPZZ_B(sve_cmphi_ppzz_b, uint8_t, >)
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DO_CMP_PPZZ_H(sve_cmphi_ppzz_h, uint16_t, >)
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DO_CMP_PPZZ_S(sve_cmphi_ppzz_s, uint32_t, >)
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DO_CMP_PPZZ_D(sve_cmphi_ppzz_d, uint64_t, >)
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DO_CMP_PPZZ_B(sve_cmphs_ppzz_b, uint8_t, >=)
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DO_CMP_PPZZ_H(sve_cmphs_ppzz_h, uint16_t, >=)
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DO_CMP_PPZZ_S(sve_cmphs_ppzz_s, uint32_t, >=)
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DO_CMP_PPZZ_D(sve_cmphs_ppzz_d, uint64_t, >=)
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#undef DO_CMP_PPZZ_B
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#undef DO_CMP_PPZZ_H
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#undef DO_CMP_PPZZ_S
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#undef DO_CMP_PPZZ_D
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#undef DO_CMP_PPZZ
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/* Similar, but the second source is "wide". */
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#define DO_CMP_PPZW(NAME, TYPE, TYPEW, OP, H, MASK) \
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uint32_t HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \
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{ \
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intptr_t opr_sz = simd_oprsz(desc); \
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uint32_t flags = PREDTEST_INIT; \
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intptr_t i = opr_sz; \
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do { \
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uint64_t out = 0, pg; \
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do { \
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TYPEW mm = *(TYPEW *)(vm + i - 8); \
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do { \
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i -= sizeof(TYPE), out <<= sizeof(TYPE); \
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TYPE nn = *(TYPE *)(vn + H(i)); \
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out |= nn OP mm; \
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} while (i & 7); \
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} while (i & 63); \
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pg = *(uint64_t *)(vg + (i >> 3)) & MASK; \
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out &= pg; \
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*(uint64_t *)(vd + (i >> 3)) = out; \
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flags = iter_predtest_bwd(out, pg, flags); \
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} while (i > 0); \
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return flags; \
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}
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#define DO_CMP_PPZW_B(NAME, TYPE, TYPEW, OP) \
|
||||
DO_CMP_PPZW(NAME, TYPE, TYPEW, OP, H1, 0xffffffffffffffffull)
|
||||
#define DO_CMP_PPZW_H(NAME, TYPE, TYPEW, OP) \
|
||||
DO_CMP_PPZW(NAME, TYPE, TYPEW, OP, H1_2, 0x5555555555555555ull)
|
||||
#define DO_CMP_PPZW_S(NAME, TYPE, TYPEW, OP) \
|
||||
DO_CMP_PPZW(NAME, TYPE, TYPEW, OP, H1_4, 0x1111111111111111ull)
|
||||
|
||||
DO_CMP_PPZW_B(sve_cmpeq_ppzw_b, uint8_t, uint64_t, ==)
|
||||
DO_CMP_PPZW_H(sve_cmpeq_ppzw_h, uint16_t, uint64_t, ==)
|
||||
DO_CMP_PPZW_S(sve_cmpeq_ppzw_s, uint32_t, uint64_t, ==)
|
||||
|
||||
DO_CMP_PPZW_B(sve_cmpne_ppzw_b, uint8_t, uint64_t, !=)
|
||||
DO_CMP_PPZW_H(sve_cmpne_ppzw_h, uint16_t, uint64_t, !=)
|
||||
DO_CMP_PPZW_S(sve_cmpne_ppzw_s, uint32_t, uint64_t, !=)
|
||||
|
||||
DO_CMP_PPZW_B(sve_cmpgt_ppzw_b, int8_t, int64_t, >)
|
||||
DO_CMP_PPZW_H(sve_cmpgt_ppzw_h, int16_t, int64_t, >)
|
||||
DO_CMP_PPZW_S(sve_cmpgt_ppzw_s, int32_t, int64_t, >)
|
||||
|
||||
DO_CMP_PPZW_B(sve_cmpge_ppzw_b, int8_t, int64_t, >=)
|
||||
DO_CMP_PPZW_H(sve_cmpge_ppzw_h, int16_t, int64_t, >=)
|
||||
DO_CMP_PPZW_S(sve_cmpge_ppzw_s, int32_t, int64_t, >=)
|
||||
|
||||
DO_CMP_PPZW_B(sve_cmphi_ppzw_b, uint8_t, uint64_t, >)
|
||||
DO_CMP_PPZW_H(sve_cmphi_ppzw_h, uint16_t, uint64_t, >)
|
||||
DO_CMP_PPZW_S(sve_cmphi_ppzw_s, uint32_t, uint64_t, >)
|
||||
|
||||
DO_CMP_PPZW_B(sve_cmphs_ppzw_b, uint8_t, uint64_t, >=)
|
||||
DO_CMP_PPZW_H(sve_cmphs_ppzw_h, uint16_t, uint64_t, >=)
|
||||
DO_CMP_PPZW_S(sve_cmphs_ppzw_s, uint32_t, uint64_t, >=)
|
||||
|
||||
DO_CMP_PPZW_B(sve_cmplt_ppzw_b, int8_t, int64_t, <)
|
||||
DO_CMP_PPZW_H(sve_cmplt_ppzw_h, int16_t, int64_t, <)
|
||||
DO_CMP_PPZW_S(sve_cmplt_ppzw_s, int32_t, int64_t, <)
|
||||
|
||||
DO_CMP_PPZW_B(sve_cmple_ppzw_b, int8_t, int64_t, <=)
|
||||
DO_CMP_PPZW_H(sve_cmple_ppzw_h, int16_t, int64_t, <=)
|
||||
DO_CMP_PPZW_S(sve_cmple_ppzw_s, int32_t, int64_t, <=)
|
||||
|
||||
DO_CMP_PPZW_B(sve_cmplo_ppzw_b, uint8_t, uint64_t, <)
|
||||
DO_CMP_PPZW_H(sve_cmplo_ppzw_h, uint16_t, uint64_t, <)
|
||||
DO_CMP_PPZW_S(sve_cmplo_ppzw_s, uint32_t, uint64_t, <)
|
||||
|
||||
DO_CMP_PPZW_B(sve_cmpls_ppzw_b, uint8_t, uint64_t, <=)
|
||||
DO_CMP_PPZW_H(sve_cmpls_ppzw_h, uint16_t, uint64_t, <=)
|
||||
DO_CMP_PPZW_S(sve_cmpls_ppzw_s, uint32_t, uint64_t, <=)
|
||||
|
||||
#undef DO_CMP_PPZW_B
|
||||
#undef DO_CMP_PPZW_H
|
||||
#undef DO_CMP_PPZW_S
|
||||
#undef DO_CMP_PPZW
|
||||
|
||||
@ -33,6 +33,10 @@
|
||||
#include "trace-tcg.h"
|
||||
#include "translate-a64.h"
|
||||
|
||||
|
||||
typedef void gen_helper_gvec_flags_4(TCGv_i32, TCGv_ptr, TCGv_ptr,
|
||||
TCGv_ptr, TCGv_ptr, TCGv_i32);
|
||||
|
||||
/*
|
||||
* Helpers for extracting complex instruction fields.
|
||||
*/
|
||||
@ -2696,6 +2700,93 @@ static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
*** SVE Integer Compare - Vectors Group
|
||||
*/
|
||||
|
||||
static bool do_ppzz_flags(DisasContext *s, arg_rprr_esz *a,
|
||||
gen_helper_gvec_flags_4 *gen_fn)
|
||||
{
|
||||
TCGv_ptr pd, zn, zm, pg;
|
||||
unsigned vsz;
|
||||
TCGv_i32 t;
|
||||
|
||||
if (gen_fn == NULL) {
|
||||
return false;
|
||||
}
|
||||
if (!sve_access_check(s)) {
|
||||
return true;
|
||||
}
|
||||
|
||||
vsz = vec_full_reg_size(s);
|
||||
t = tcg_const_i32(simd_desc(vsz, vsz, 0));
|
||||
pd = tcg_temp_new_ptr();
|
||||
zn = tcg_temp_new_ptr();
|
||||
zm = tcg_temp_new_ptr();
|
||||
pg = tcg_temp_new_ptr();
|
||||
|
||||
tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd));
|
||||
tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn));
|
||||
tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm));
|
||||
tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg));
|
||||
|
||||
gen_fn(t, pd, zn, zm, pg, t);
|
||||
|
||||
tcg_temp_free_ptr(pd);
|
||||
tcg_temp_free_ptr(zn);
|
||||
tcg_temp_free_ptr(zm);
|
||||
tcg_temp_free_ptr(pg);
|
||||
|
||||
do_pred_flags(t);
|
||||
|
||||
tcg_temp_free_i32(t);
|
||||
return true;
|
||||
}
|
||||
|
||||
#define DO_PPZZ(NAME, name) \
|
||||
static bool trans_##NAME##_ppzz(DisasContext *s, arg_rprr_esz *a, \
|
||||
uint32_t insn) \
|
||||
{ \
|
||||
static gen_helper_gvec_flags_4 * const fns[4] = { \
|
||||
gen_helper_sve_##name##_ppzz_b, gen_helper_sve_##name##_ppzz_h, \
|
||||
gen_helper_sve_##name##_ppzz_s, gen_helper_sve_##name##_ppzz_d, \
|
||||
}; \
|
||||
return do_ppzz_flags(s, a, fns[a->esz]); \
|
||||
}
|
||||
|
||||
DO_PPZZ(CMPEQ, cmpeq)
|
||||
DO_PPZZ(CMPNE, cmpne)
|
||||
DO_PPZZ(CMPGT, cmpgt)
|
||||
DO_PPZZ(CMPGE, cmpge)
|
||||
DO_PPZZ(CMPHI, cmphi)
|
||||
DO_PPZZ(CMPHS, cmphs)
|
||||
|
||||
#undef DO_PPZZ
|
||||
|
||||
#define DO_PPZW(NAME, name) \
|
||||
static bool trans_##NAME##_ppzw(DisasContext *s, arg_rprr_esz *a, \
|
||||
uint32_t insn) \
|
||||
{ \
|
||||
static gen_helper_gvec_flags_4 * const fns[4] = { \
|
||||
gen_helper_sve_##name##_ppzw_b, gen_helper_sve_##name##_ppzw_h, \
|
||||
gen_helper_sve_##name##_ppzw_s, NULL \
|
||||
}; \
|
||||
return do_ppzz_flags(s, a, fns[a->esz]); \
|
||||
}
|
||||
|
||||
DO_PPZW(CMPEQ, cmpeq)
|
||||
DO_PPZW(CMPNE, cmpne)
|
||||
DO_PPZW(CMPGT, cmpgt)
|
||||
DO_PPZW(CMPGE, cmpge)
|
||||
DO_PPZW(CMPHI, cmphi)
|
||||
DO_PPZW(CMPHS, cmphs)
|
||||
DO_PPZW(CMPLT, cmplt)
|
||||
DO_PPZW(CMPLE, cmple)
|
||||
DO_PPZW(CMPLO, cmplo)
|
||||
DO_PPZW(CMPLS, cmpls)
|
||||
|
||||
#undef DO_PPZW
|
||||
|
||||
/*
|
||||
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user