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target/arm: Implement FEAT_IDST

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The Armv8.4 feature FEAT_IDST specifies that exceptions generated by
read accesses to the feature ID space should report a syndrome code
of 0x18 (EC_SYSTEMREGISTERTRAP) rather than 0x00 (EC_UNCATEGORIZED).
The feature ID space is defined to be:
 op0 == 3, op1 == {0,1,3}, CRn == 0, CRm == {0-7}, op2 == {0-7}

In our implementation we might return the EC_UNCATEGORIZED syndrome
value for a system register access in four cases:
 * no reginfo struct in the hashtable
 * cp_access_ok() fails (ie ri->access doesn't permit the access)
 * ri->accessfn returns CP_ACCESS_TRAP_UNCATEGORIZED at runtime
 * ri->type includes ARM_CP_RAISES_EXC, and the readfn raises
   an UNDEF exception at runtime

We have very few regdefs that set ARM_CP_RAISES_EXC, and none of
them are in the feature ID space. (In the unlikely event that any
are added in future they would need to take care of setting the
correct syndrome themselves.) This patch deals with the other
three cases, and enables FEAT_IDST for AArch64 -cpu max.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220509155457.3560724-1-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-05-09 16:54:57 +01:00
parent e04bf5a793
commit 75662f36e3
6 changed files with 66 additions and 2 deletions
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1
docs/system/arm/emulation.rst
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@ -31,6 +31,7 @@ the following architecture extensions:
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
- FEAT_HPDS (Hierarchical permission disables)
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
- FEAT_IDST (ID space trap handling)
- FEAT_IESB (Implicit error synchronization event)
- FEAT_JSCVT (JavaScript conversion instructions)
- FEAT_LOR (Limited ordering regions)

24
target/arm/cpregs.h
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@ -461,4 +461,28 @@ static inline bool cp_access_ok(int current_el,
/* Raw read of a coprocessor register (as needed for migration, etc) */
uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
/*
* Return true if the cp register encoding is in the "feature ID space" as
* defined by FEAT_IDST (and thus should be reported with ER_ELx.EC
* as EC_SYSTEMREGISTERTRAP rather than EC_UNCATEGORIZED).
*/
static inline bool arm_cpreg_encoding_in_idspace(uint8_t opc0, uint8_t opc1,
uint8_t opc2,
uint8_t crn, uint8_t crm)
{
return opc0 == 3 && (opc1 == 0 || opc1 == 1 || opc1 == 3) &&
crn == 0 && crm < 8;
}
/*
* As arm_cpreg_encoding_in_idspace(), but take the encoding from an
* ARMCPRegInfo.
*/
static inline bool arm_cpreg_in_idspace(const ARMCPRegInfo *ri)
{
return ri->state == ARM_CP_STATE_AA64 &&
arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2,
ri->crn, ri->crm);
}
#endif /* TARGET_ARM_CPREGS_H */

5
target/arm/cpu.h
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@ -3946,6 +3946,11 @@ static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
}
static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
}
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;

1
target/arm/cpu64.c
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@ -928,6 +928,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */
t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 1); /* FEAT_IDST */
t = FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */

9
target/arm/op_helper.c
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@ -631,6 +631,7 @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno)
void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
uint32_t isread)
{
ARMCPU *cpu = env_archcpu(env);
const ARMCPRegInfo *ri = rip;
CPAccessResult res = CP_ACCESS_OK;
int target_el;
@ -674,6 +675,14 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
case CP_ACCESS_TRAP:
break;
case CP_ACCESS_TRAP_UNCATEGORIZED:
if (cpu_isar_feature(aa64_ids, cpu) && isread &&
arm_cpreg_in_idspace(ri)) {
/*
* FEAT_IDST says this should be reported as EC_SYSTEMREGISTERTRAP,
* not EC_UNCATEGORIZED
*/
break;
}
syndrome = syn_uncategorized();
break;
default:

28
target/arm/translate-a64.c
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@ -1795,6 +1795,30 @@ static void gen_set_nzcv(TCGv_i64 tcg_rt)
tcg_temp_free_i32(nzcv);
}
static void gen_sysreg_undef(DisasContext *s, bool isread,
uint8_t op0, uint8_t op1, uint8_t op2,
uint8_t crn, uint8_t crm, uint8_t rt)
{
/*
* Generate code to emit an UNDEF with correct syndrome
* information for a failed system register access.
* This is EC_UNCATEGORIZED (ie a standard UNDEF) in most cases,
* but if FEAT_IDST is implemented then read accesses to registers
* in the feature ID space are reported with the EC_SYSTEMREGISTERTRAP
* syndrome.
*/
uint32_t syndrome;
if (isread && dc_isar_feature(aa64_ids, s) &&
arm_cpreg_encoding_in_idspace(op0, op1, op2, crn, crm)) {
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
} else {
syndrome = syn_uncategorized();
}
gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syndrome,
default_exception_el(s));
}
/* MRS - move from system register
* MSR (register) - move to system register
* SYS
@ -1820,13 +1844,13 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
"system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
isread ? "read" : "write", op0, op1, crn, crm, op2);
unallocated_encoding(s);
gen_sysreg_undef(s, isread, op0, op1, op2, crn, crm, rt);
return;
}
/* Check access permissions */
if (!cp_access_ok(s->current_el, ri, isread)) {
unallocated_encoding(s);
gen_sysreg_undef(s, isread, op0, op1, op2, crn, crm, rt);
return;
}