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tcg/arm: Implement TCG_TARGET_HAS_mul_vec

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-09-05 12:30:17 -07:00
parent d4c4e9c51b
commit 752b17693e
2 changed files with 7 additions and 1 deletions
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6
tcg/arm/tcg-target.c.inc
View File

@ -183,6 +183,7 @@ typedef enum {
INSN_VORN = 0xf2300110,
INSN_VORR = 0xf2200110,
INSN_VSUB = 0xf3000800,
INSN_VMUL = 0xf2000910,
INSN_VABS = 0xf3b10300,
INSN_VMVN = 0xf3b00580,
@ -2394,6 +2395,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
return C_O1_I1(w, w);
case INDEX_op_dup2_vec:
case INDEX_op_add_vec:
case INDEX_op_mul_vec:
case INDEX_op_sub_vec:
case INDEX_op_xor_vec:
return C_O1_I2(w, w, w);
@ -2755,6 +2757,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_add_vec:
tcg_out_vreg3(s, INSN_VADD, q, vece, a0, a1, a2);
return;
case INDEX_op_mul_vec:
tcg_out_vreg3(s, INSN_VMUL, q, vece, a0, a1, a2);
return;
case INDEX_op_sub_vec:
tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2);
return;
@ -2871,6 +2876,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
return 1;
case INDEX_op_abs_vec:
case INDEX_op_cmp_vec:
case INDEX_op_mul_vec:
case INDEX_op_neg_vec:
return vece < MO_64;
default:

2
tcg/arm/tcg-target.h
View File

@ -166,7 +166,7 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_HAS_bitsel_vec 0