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Sparc32: move sparc32_dma init to sun4m.c

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Also connect ESP and Lance reset signals to DMA.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2009-08-08 21:43:12 +00:00
parent d95d8f1c11
commit 74ff8d90a1
4 changed files with 43 additions and 43 deletions
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1
hw/esp.c
View File

@ -667,6 +667,7 @@ void esp_init(target_phys_addr_t espaddr, int it_shift,
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, irq);
sysbus_mmio_map(s, 0, espaddr);
*reset = qdev_get_gpio_in(dev, 0);
}
static void esp_init1(SysBusDevice *dev)

22
hw/sparc32_dma.c
View File

@ -244,27 +244,6 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
void *iommu, qemu_irq *dev_irq, qemu_irq **reset)
{
DeviceState *dev;
SysBusDevice *s;
DMAState *d;
dev = qdev_create(NULL, "sparc32_dma");
qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, parent_irq);
*dev_irq = qdev_get_gpio_in(dev, 0);
sysbus_mmio_map(s, 0, daddr);
d = FROM_SYSBUS(DMAState, s);
*reset = &d->dev_reset;
return d;
}
static void sparc32_dma_init1(SysBusDevice *dev)
{
DMAState *s = FROM_SYSBUS(DMAState, dev);
@ -279,6 +258,7 @@ static void sparc32_dma_init1(SysBusDevice *dev)
qemu_register_reset(dma_reset, s);
qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
qdev_init_gpio_out(&dev->qdev, &s->dev_reset, 1);
}
static SysBusDeviceInfo sparc32_dma_info = {

2
hw/sparc32_dma.h
View File

@ -2,8 +2,6 @@
#define SPARC32_DMA_H
/* sparc32_dma.c */
void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
void *iommu, qemu_irq *dev_irq, qemu_irq **reset);
void ledma_memory_read(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int do_bswap);
void ledma_memory_write(void *opaque, target_phys_addr_t addr,

61
hw/sun4m.c
View File

@ -364,12 +364,30 @@ static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
return s;
}
static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
void *dma_opaque, qemu_irq irq, qemu_irq *reset)
static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
void *iommu, qemu_irq *dev_irq)
{
DeviceState *dev;
SysBusDevice *s;
dev = qdev_create(NULL, "sparc32_dma");
qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_connect_irq(s, 0, parent_irq);
*dev_irq = qdev_get_gpio_in(dev, 0);
sysbus_mmio_map(s, 0, daddr);
return s;
}
static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
void *dma_opaque, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *s;
qemu_irq reset;
qemu_check_nic_model(&nd_table[0], "lance");
dev = qdev_create(NULL, "lance");
@ -379,7 +397,8 @@ static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
s = sysbus_from_qdev(dev);
sysbus_mmio_map(s, 0, leaddr);
sysbus_connect_irq(s, 0, irq);
*reset = qdev_get_gpio_in(dev, 0);
reset = qdev_get_gpio_in(dev, 0);
qdev_connect_gpio_out(dma_opaque, 0, reset);
}
static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
@ -735,7 +754,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
void *iommu, *espdma, *ledma, *nvram;
qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
espdma_irq, ledma_irq;
qemu_irq *esp_reset, *le_reset;
qemu_irq esp_reset;
qemu_irq fdc_tc;
qemu_irq *cpu_halt;
unsigned long kernel_size;
@ -781,11 +800,10 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
slavio_irq[30]);
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
iommu, &espdma_irq, &esp_reset);
iommu, &espdma_irq);
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
slavio_irq[16], iommu, &ledma_irq,
&le_reset);
slavio_irq[16], iommu, &ledma_irq);
if (graphic_depth != 8 && graphic_depth != 24) {
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
@ -794,7 +812,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
@ -831,9 +849,11 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
exit(1);
}
esp_reset = qdev_get_gpio_in(espdma, 0);
esp_init(hwdef->esp_base, 2,
espdma_memory_read, espdma_memory_write,
espdma, espdma_irq, esp_reset);
espdma, espdma_irq, &esp_reset);
if (hwdef->cs_base) {
sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
@ -1354,7 +1374,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
espdma_irq, ledma_irq;
qemu_irq *esp_reset, *le_reset;
qemu_irq esp_reset;
unsigned long kernel_size;
void *fw_cfg;
DeviceState *dev;
@ -1391,10 +1411,10 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
sbi_irq[0]);
espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
iounits[0], &espdma_irq, &esp_reset);
iounits[0], &espdma_irq);
ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
iounits[0], &ledma_irq, &le_reset);
iounits[0], &ledma_irq);
if (graphic_depth != 8 && graphic_depth != 24) {
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
@ -1403,7 +1423,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
@ -1421,9 +1441,10 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
exit(1);
}
esp_reset = qdev_get_gpio_in(espdma, 0);
esp_init(hwdef->esp_base, 2,
espdma_memory_read, espdma_memory_write,
espdma, espdma_irq, esp_reset);
espdma, espdma_irq, &esp_reset);
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
RAM_size);
@ -1540,7 +1561,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
CPUState *env;
void *iommu, *espdma, *ledma, *nvram;
qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
qemu_irq *esp_reset, *le_reset;
qemu_irq esp_reset;
qemu_irq fdc_tc;
unsigned long kernel_size;
BlockDriverState *fd[MAX_FD];
@ -1570,11 +1591,10 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
slavio_irq[1]);
espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
iommu, &espdma_irq, &esp_reset);
iommu, &espdma_irq);
ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
slavio_irq[3], iommu, &ledma_irq,
&le_reset);
slavio_irq[3], iommu, &ledma_irq);
if (graphic_depth != 8 && graphic_depth != 24) {
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
@ -1583,7 +1603,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
@ -1614,9 +1634,10 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
exit(1);
}
esp_reset = qdev_get_gpio_in(espdma, 0);
esp_init(hwdef->esp_base, 2,
espdma_memory_read, espdma_memory_write,
espdma, espdma_irq, esp_reset);
espdma, espdma_irq, &esp_reset);
kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
RAM_size);