Fix PowerMac NVRAM device.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3521 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer 2007-11-04 01:16:04 +00:00
parent f3e3285dcd
commit 74e9115560
5 changed files with 33 additions and 16 deletions

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@ -26,6 +26,9 @@
#include "ppc_mac.h" #include "ppc_mac.h"
struct MacIONVRAMState { struct MacIONVRAMState {
target_phys_addr_t mem_base;
target_phys_addr_t size;
int mem_index;
uint8_t data[0x2000]; uint8_t data[0x2000];
}; };
@ -58,6 +61,8 @@ static void macio_nvram_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value) target_phys_addr_t addr, uint32_t value)
{ {
MacIONVRAMState *s = opaque; MacIONVRAMState *s = opaque;
addr -= s->mem_base;
addr = (addr >> 4) & 0x1fff; addr = (addr >> 4) & 0x1fff;
s->data[addr] = value; s->data[addr] = value;
// printf("macio_nvram_writeb %04x = %02x\n", addr, value); // printf("macio_nvram_writeb %04x = %02x\n", addr, value);
@ -68,6 +73,7 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
MacIONVRAMState *s = opaque; MacIONVRAMState *s = opaque;
uint32_t value; uint32_t value;
addr -= s->mem_base;
addr = (addr >> 4) & 0x1fff; addr = (addr >> 4) & 0x1fff;
value = s->data[addr]; value = s->data[addr];
// printf("macio_nvram_readb %04x = %02x\n", addr, value); // printf("macio_nvram_readb %04x = %02x\n", addr, value);
@ -87,17 +93,29 @@ static CPUReadMemoryFunc *nvram_read[] = {
&macio_nvram_readb, &macio_nvram_readb,
}; };
MacIONVRAMState *macio_nvram_init (int *mem_index) MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size)
{ {
MacIONVRAMState *s; MacIONVRAMState *s;
s = qemu_mallocz(sizeof(MacIONVRAMState)); s = qemu_mallocz(sizeof(MacIONVRAMState));
if (!s) if (!s)
return NULL; return NULL;
*mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s); s->size = size;
s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
*mem_index = s->mem_index;
return s; return s;
} }
void macio_nvram_map (void *opaque, target_phys_addr_t mem_base)
{
MacIONVRAMState *s;
s = opaque;
s->mem_base = mem_base;
cpu_register_physical_memory(mem_base, s->size, s->mem_index);
}
static uint8_t nvram_chksum (const uint8_t *buf, int n) static uint8_t nvram_chksum (const uint8_t *buf, int n)
{ {
int sum, i; int sum, i;

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@ -31,7 +31,7 @@ struct macio_state_t {
int pic_mem_index; int pic_mem_index;
int dbdma_mem_index; int dbdma_mem_index;
int cuda_mem_index; int cuda_mem_index;
int nvram_mem_index; void *nvram;
int nb_ide; int nb_ide;
int ide_mem_index[4]; int ide_mem_index[4];
}; };
@ -68,14 +68,12 @@ static void macio_map (PCIDevice *pci_dev, int region_num,
macio_state->ide_mem_index[i]); macio_state->ide_mem_index[i]);
} }
} }
if (macio_state->nvram_mem_index >= 0) { if (macio_state->nvram != NULL)
cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_map(macio_state->nvram, addr + 0x60000);
macio_state->nvram_mem_index);
}
} }
void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
int dbdma_mem_index, int cuda_mem_index, int nvram_mem_index, int dbdma_mem_index, int cuda_mem_index, void *nvram,
int nb_ide, int *ide_mem_index) int nb_ide, int *ide_mem_index)
{ {
PCIDevice *d; PCIDevice *d;
@ -90,7 +88,7 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
macio_state->pic_mem_index = pic_mem_index; macio_state->pic_mem_index = pic_mem_index;
macio_state->dbdma_mem_index = dbdma_mem_index; macio_state->dbdma_mem_index = dbdma_mem_index;
macio_state->cuda_mem_index = cuda_mem_index; macio_state->cuda_mem_index = cuda_mem_index;
macio_state->nvram_mem_index = nvram_mem_index; macio_state->nvram = nvram;
if (nb_ide > 4) if (nb_ide > 4)
nb_ide = 4; nb_ide = 4;
macio_state->nb_ide = nb_ide; macio_state->nb_ide = nb_ide;

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@ -264,7 +264,7 @@ static void ppc_core99_init (int ram_size, int vga_ram_size,
dbdma_init(&dbdma_mem_index); dbdma_init(&dbdma_mem_index);
macio_init(pci_bus, 0x0022, 0, pic_mem_index, dbdma_mem_index, macio_init(pci_bus, 0x0022, 0, pic_mem_index, dbdma_mem_index,
cuda_mem_index, -1, 2, ide_mem_index); cuda_mem_index, NULL, 2, ide_mem_index);
if (usb_enabled) { if (usb_enabled) {
usb_ohci_init_pci(pci_bus, 3, -1); usb_ohci_init_pci(pci_bus, 3, -1);
@ -274,9 +274,9 @@ static void ppc_core99_init (int ram_size, int vga_ram_size,
graphic_depth = 15; graphic_depth = 15;
#if 0 /* XXX: this is ugly but needed for now, or OHW won't boot */ #if 0 /* XXX: this is ugly but needed for now, or OHW won't boot */
/* The NewWorld NVRAM is not located in the MacIO device */ /* The NewWorld NVRAM is not located in the MacIO device */
nvr = macio_nvram_init(&nvram_mem_index); nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
pmac_format_nvram_partition(nvr, 0x2000); pmac_format_nvram_partition(nvr, 0x2000);
cpu_register_physical_memory(0xFFF04000, 0x20000, nvram_mem_index); macio_nvram_map(nvr, 0xFFF04000);
nvram.opaque = nvr; nvram.opaque = nvr;
nvram.read_fn = &macio_nvram_read; nvram.read_fn = &macio_nvram_read;
nvram.write_fn = &macio_nvram_write; nvram.write_fn = &macio_nvram_write;

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@ -43,7 +43,7 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq);
/* MacIO */ /* MacIO */
void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index, void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
int dbdma_mem_index, int cuda_mem_index, int nvram_mem_index, int dbdma_mem_index, int cuda_mem_index, void *nvram,
int nb_ide, int *ide_mem_index); int nb_ide, int *ide_mem_index);
/* NewWorld PowerMac IDE */ /* NewWorld PowerMac IDE */
@ -62,7 +62,8 @@ PCIBus *pci_pmac_init(qemu_irq *pic);
/* Mac NVRAM */ /* Mac NVRAM */
typedef struct MacIONVRAMState MacIONVRAMState; typedef struct MacIONVRAMState MacIONVRAMState;
MacIONVRAMState *macio_nvram_init (int *mem_index); MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size);
void macio_nvram_map (void *opaque, target_phys_addr_t mem_base);
void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len); void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
uint32_t macio_nvram_read (void *opaque, uint32_t addr); uint32_t macio_nvram_read (void *opaque, uint32_t addr);
void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val); void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);

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@ -271,13 +271,13 @@ static void ppc_heathrow_init (int ram_size, int vga_ram_size,
adb_kbd_init(&adb_bus); adb_kbd_init(&adb_bus);
adb_mouse_init(&adb_bus); adb_mouse_init(&adb_bus);
nvr = macio_nvram_init(&nvram_mem_index); nvr = macio_nvram_init(&nvram_mem_index, 0x2000);
pmac_format_nvram_partition(nvr, 0x2000); pmac_format_nvram_partition(nvr, 0x2000);
dbdma_init(&dbdma_mem_index); dbdma_init(&dbdma_mem_index);
macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index, macio_init(pci_bus, 0x0017, 1, pic_mem_index, dbdma_mem_index,
cuda_mem_index, nvram_mem_index, 0, NULL); cuda_mem_index, nvr, 0, NULL);
if (usb_enabled) { if (usb_enabled) {
usb_ohci_init_pci(pci_bus, 3, -1); usb_ohci_init_pci(pci_bus, 3, -1);