qemu-sparc queue
-----BEGIN PGP SIGNATURE----- iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmCSSUkeHG1hcmsuY2F2 ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIfqAEIAJRq2gVd3QRH7zVp 74wDnG/ybBM3/jCswcs9HnXhWpXqACTw+tK6iu49VUbfPgZF6GdGsUIUUc56DGnV w9s95hVDLYOmE9przGqImGD8XQBnf9yIUbWnX1y0l2khJtDv/7rCVk3XzztP6wQs wc0DWGxXbu/O90T9NiRh4GkzLo/fDtEscCqGir3XkqYllR+8FfwD7s5bcAsjqOHD hGTsvXfuRRcjFoXUcd2ysRmVmuQyLi2ija7EH3KsWY1JvXTxu/QsS/pp0kkh+aF+ 2HwRgyV1sLE1UA5yD+4iNnM5C+nAT9TGp0Aqpd0Fms4uX3V7LjZWZi/0V76K3RgS PU8aB8M= =REjm -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20210505' into staging qemu-sparc queue # gpg: Signature made Wed 05 May 2021 08:29:13 BST # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full] # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * remotes/mcayland/tags/qemu-sparc-20210505: hw/sparc*: Move cpu_check_irqs() to target/sparc/ hw/sparc64: Fix code style for checkpatch.pl hw/sparc64: Remove unused "hw/char/serial.h" header hw/sparc: Allow building without the leon3 machine hw/sparc/sun4m: Move each sun4m_hwdef definition in its class_init hw/sparc/sun4m: Fix code style for checkpatch.pl hw/sparc/sun4m: Register machine types in sun4m_machine_types[] hw/sparc/sun4m: Factor out sun4m_machine_class_init() hw/sparc/sun4m: Introduce Sun4mMachineClass hw/sparc/sun4m: Have sun4m machines inherit new TYPE_SUN4M_MACHINE Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
74e31681ba
@ -136,7 +136,36 @@ static void main_cpu_reset(void *opaque)
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env->regbase[6] = s->sp;
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}
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void leon3_irq_ack(void *irq_manager, int intno)
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static void leon3_cache_control_int(CPUSPARCState *env)
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{
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uint32_t state = 0;
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if (env->cache_control & CACHE_CTRL_IF) {
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/* Instruction cache state */
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state = env->cache_control & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
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trace_int_helper_icache_freeze();
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}
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env->cache_control &= ~CACHE_STATE_MASK;
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env->cache_control |= state;
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}
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if (env->cache_control & CACHE_CTRL_DF) {
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/* Data cache state */
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state = (env->cache_control >> 2) & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
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trace_int_helper_dcache_freeze();
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}
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env->cache_control &= ~(CACHE_STATE_MASK << 2);
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env->cache_control |= (state << 2);
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}
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}
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static void leon3_irq_ack(void *irq_manager, int intno)
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{
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grlib_irqmp_ack((DeviceState *)irq_manager, intno);
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}
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@ -180,6 +209,12 @@ static void leon3_set_pil_in(void *opaque, int n, int level)
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}
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}
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static void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
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{
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leon3_irq_ack(irq_manager, intno);
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leon3_cache_control_int(env);
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}
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static void leon3_generic_hw_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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491
hw/sparc/sun4m.c
491
hw/sparc/sun4m.c
@ -107,6 +107,17 @@ struct sun4m_hwdef {
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uint8_t nvram_machine_id;
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};
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struct Sun4mMachineClass {
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/*< private >*/
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MachineClass parent_obj;
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/*< public >*/
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const struct sun4m_hwdef *hwdef;
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};
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typedef struct Sun4mMachineClass Sun4mMachineClass;
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#define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common")
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DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE)
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const char *fw_cfg_arch_key_name(uint16_t key)
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{
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static const struct {
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@ -159,38 +170,6 @@ static void nvram_init(Nvram *nvram, uint8_t *macaddr,
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}
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}
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void cpu_check_irqs(CPUSPARCState *env)
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{
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CPUState *cs;
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/* We should be holding the BQL before we mess with IRQs */
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g_assert(qemu_mutex_iothread_locked());
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if (env->pil_in && (env->interrupt_index == 0 ||
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i;
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for (i = 15; i > 0; i--) {
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if (env->pil_in & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i;
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if (old_interrupt != env->interrupt_index) {
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cs = env_cpu(env);
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trace_sun4m_cpu_interrupt(i);
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
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cs = env_cpu(env);
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trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
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env->interrupt_index = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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static void cpu_kick_irq(SPARCCPU *cpu)
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{
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CPUSPARCState *env = &cpu->env;
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@ -837,9 +816,9 @@ static void dummy_fdc_tc(void *opaque, int irq, int level)
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{
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}
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static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
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MachineState *machine)
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static void sun4m_hw_init(MachineState *machine)
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{
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const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef;
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DeviceState *slavio_intctl;
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unsigned int i;
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Nvram *nvram;
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@ -1127,9 +1106,22 @@ enum {
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ss600mp_id,
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};
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static const struct sun4m_hwdef sun4m_hwdefs[] = {
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/* SS-5 */
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{
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static void sun4m_machine_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->init = sun4m_hw_init;
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mc->block_default_type = IF_SCSI;
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mc->default_boot_order = "c";
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mc->default_display = "tcx";
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mc->default_ram_id = "sun4m.ram";
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}
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static void ss5_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
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static const struct sun4m_hwdef ss5_hwdef = {
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.iommu_base = 0x10000000,
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.iommu_pad_base = 0x10004000,
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.iommu_pad_len = 0x0fffb000,
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@ -1154,9 +1146,19 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.machine_id = ss5_id,
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.iommu_version = 0x05000000,
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.max_mem = 0x10000000,
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},
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/* SS-10 */
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{
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};
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mc->desc = "Sun4m platform, SPARCstation 5";
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mc->is_default = true;
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mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
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smc->hwdef = &ss5_hwdef;
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}
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static void ss10_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
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static const struct sun4m_hwdef ss10_hwdef = {
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.iommu_base = 0xfe0000000ULL,
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.tcx_base = 0xe20000000ULL,
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.slavio_base = 0xff0000000ULL,
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@ -1170,18 +1172,28 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.dma_base = 0xef0400000ULL,
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.esp_base = 0xef0800000ULL,
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.le_base = 0xef0c00000ULL,
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.apc_base = 0xefa000000ULL, // XXX should not exist
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.apc_base = 0xefa000000ULL, /* XXX should not exist */
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.aux1_base = 0xff1800000ULL,
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.aux2_base = 0xff1a01000ULL,
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x10000000, // version 0, implementation 1
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.ecc_version = 0x10000000, /* version 0, implementation 1 */
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.nvram_machine_id = 0x72,
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.machine_id = ss10_id,
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.iommu_version = 0x03000000,
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.max_mem = 0xf00000000ULL,
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},
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/* SS-600MP */
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{
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};
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mc->desc = "Sun4m platform, SPARCstation 10";
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mc->max_cpus = 4;
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mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
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smc->hwdef = &ss10_hwdef;
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}
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static void ss600mp_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
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static const struct sun4m_hwdef ss600mp_hwdef = {
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.iommu_base = 0xfe0000000ULL,
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.tcx_base = 0xe20000000ULL,
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.slavio_base = 0xff0000000ULL,
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@ -1193,18 +1205,28 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.dma_base = 0xef0081000ULL,
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.esp_base = 0xef0080000ULL,
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.le_base = 0xef0060000ULL,
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.apc_base = 0xefa000000ULL, // XXX should not exist
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.apc_base = 0xefa000000ULL, /* XXX should not exist */
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.aux1_base = 0xff1800000ULL,
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.aux2_base = 0xff1a01000ULL, // XXX should not exist
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.aux2_base = 0xff1a01000ULL, /* XXX should not exist */
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x00000000, // version 0, implementation 0
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.ecc_version = 0x00000000, /* version 0, implementation 0 */
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.nvram_machine_id = 0x71,
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.machine_id = ss600mp_id,
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.iommu_version = 0x01000000,
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.max_mem = 0xf00000000ULL,
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},
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/* SS-20 */
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{
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};
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mc->desc = "Sun4m platform, SPARCserver 600MP";
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mc->max_cpus = 4;
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mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
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smc->hwdef = &ss600mp_hwdef;
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}
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static void ss20_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
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static const struct sun4m_hwdef ss20_hwdef = {
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.iommu_base = 0xfe0000000ULL,
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.tcx_base = 0xe20000000ULL,
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.slavio_base = 0xff0000000ULL,
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@ -1219,7 +1241,7 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.esp_base = 0xef0800000ULL,
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.le_base = 0xef0c00000ULL,
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.bpp_base = 0xef4800000ULL,
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.apc_base = 0xefa000000ULL, // XXX should not exist
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.apc_base = 0xefa000000ULL, /* XXX should not exist */
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.aux1_base = 0xff1800000ULL,
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.aux2_base = 0xff1a01000ULL,
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.dbri_base = 0xee0000000ULL,
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@ -1238,14 +1260,24 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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}
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},
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.ecc_base = 0xf00000000ULL,
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.ecc_version = 0x20000000, // version 0, implementation 2
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.ecc_version = 0x20000000, /* version 0, implementation 2 */
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.nvram_machine_id = 0x72,
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.machine_id = ss20_id,
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.iommu_version = 0x13000000,
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.max_mem = 0xf00000000ULL,
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},
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/* Voyager */
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{
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};
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mc->desc = "Sun4m platform, SPARCstation 20";
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mc->max_cpus = 4;
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mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
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smc->hwdef = &ss20_hwdef;
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}
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static void voyager_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
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static const struct sun4m_hwdef voyager_hwdef = {
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.iommu_base = 0x10000000,
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.tcx_base = 0x50000000,
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.slavio_base = 0x70000000,
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@ -1259,16 +1291,25 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.dma_base = 0x78400000,
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.esp_base = 0x78800000,
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.le_base = 0x78c00000,
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.apc_base = 0x71300000, // pmc
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.apc_base = 0x71300000, /* pmc */
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.aux1_base = 0x71900000,
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.aux2_base = 0x71910000,
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.nvram_machine_id = 0x80,
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.machine_id = vger_id,
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.iommu_version = 0x05000000,
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.max_mem = 0x10000000,
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},
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/* LX */
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{
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};
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mc->desc = "Sun4m platform, SPARCstation Voyager";
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mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
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smc->hwdef = &voyager_hwdef;
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}
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static void ss_lx_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
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static const struct sun4m_hwdef ss_lx_hwdef = {
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.iommu_base = 0x10000000,
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.iommu_pad_base = 0x10004000,
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.iommu_pad_len = 0x0fffb000,
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@ -1290,9 +1331,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
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.machine_id = lx_id,
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.iommu_version = 0x04000000,
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.max_mem = 0x10000000,
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},
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/* SS-4 */
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{
|
||||
};
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|
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mc->desc = "Sun4m platform, SPARCstation LX";
|
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mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
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||||
smc->hwdef = &ss_lx_hwdef;
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}
|
||||
|
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static void ss4_class_init(ObjectClass *oc, void *data)
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{
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||||
MachineClass *mc = MACHINE_CLASS(oc);
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Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
|
||||
static const struct sun4m_hwdef ss4_hwdef = {
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.iommu_base = 0x10000000,
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.tcx_base = 0x50000000,
|
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.cs_base = 0x6c000000,
|
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@ -1314,9 +1364,18 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
|
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.machine_id = ss4_id,
|
||||
.iommu_version = 0x05000000,
|
||||
.max_mem = 0x10000000,
|
||||
},
|
||||
/* SPARCClassic */
|
||||
{
|
||||
};
|
||||
|
||||
mc->desc = "Sun4m platform, SPARCstation 4";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
|
||||
smc->hwdef = &ss4_hwdef;
|
||||
}
|
||||
|
||||
static void scls_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
|
||||
static const struct sun4m_hwdef scls_hwdef = {
|
||||
.iommu_base = 0x10000000,
|
||||
.tcx_base = 0x50000000,
|
||||
.slavio_base = 0x70000000,
|
||||
@ -1337,11 +1396,20 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
|
||||
.machine_id = scls_id,
|
||||
.iommu_version = 0x05000000,
|
||||
.max_mem = 0x10000000,
|
||||
},
|
||||
/* SPARCbook */
|
||||
{
|
||||
};
|
||||
|
||||
mc->desc = "Sun4m platform, SPARCClassic";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
|
||||
smc->hwdef = &scls_hwdef;
|
||||
}
|
||||
|
||||
static void sbook_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc);
|
||||
static const struct sun4m_hwdef sbook_hwdef = {
|
||||
.iommu_base = 0x10000000,
|
||||
.tcx_base = 0x50000000, // XXX
|
||||
.tcx_base = 0x50000000, /* XXX */
|
||||
.slavio_base = 0x70000000,
|
||||
.ms_kb_base = 0x71000000,
|
||||
.serial_base = 0x71100000,
|
||||
@ -1360,254 +1428,67 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
|
||||
.machine_id = sbook_id,
|
||||
.iommu_version = 0x05000000,
|
||||
.max_mem = 0x10000000,
|
||||
},
|
||||
};
|
||||
|
||||
/* SPARCstation 5 hardware initialisation */
|
||||
static void ss5_init(MachineState *machine)
|
||||
{
|
||||
sun4m_hw_init(&sun4m_hwdefs[0], machine);
|
||||
}
|
||||
|
||||
/* SPARCstation 10 hardware initialisation */
|
||||
static void ss10_init(MachineState *machine)
|
||||
{
|
||||
sun4m_hw_init(&sun4m_hwdefs[1], machine);
|
||||
}
|
||||
|
||||
/* SPARCserver 600MP hardware initialisation */
|
||||
static void ss600mp_init(MachineState *machine)
|
||||
{
|
||||
sun4m_hw_init(&sun4m_hwdefs[2], machine);
|
||||
}
|
||||
|
||||
/* SPARCstation 20 hardware initialisation */
|
||||
static void ss20_init(MachineState *machine)
|
||||
{
|
||||
sun4m_hw_init(&sun4m_hwdefs[3], machine);
|
||||
}
|
||||
|
||||
/* SPARCstation Voyager hardware initialisation */
|
||||
static void vger_init(MachineState *machine)
|
||||
{
|
||||
sun4m_hw_init(&sun4m_hwdefs[4], machine);
|
||||
}
|
||||
|
||||
/* SPARCstation LX hardware initialisation */
|
||||
static void ss_lx_init(MachineState *machine)
|
||||
{
|
||||
sun4m_hw_init(&sun4m_hwdefs[5], machine);
|
||||
}
|
||||
|
||||
/* SPARCstation 4 hardware initialisation */
|
||||
static void ss4_init(MachineState *machine)
|
||||
{
|
||||
sun4m_hw_init(&sun4m_hwdefs[6], machine);
|
||||
}
|
||||
|
||||
/* SPARCClassic hardware initialisation */
|
||||
static void scls_init(MachineState *machine)
|
||||
{
|
||||
sun4m_hw_init(&sun4m_hwdefs[7], machine);
|
||||
}
|
||||
|
||||
/* SPARCbook hardware initialisation */
|
||||
static void sbook_init(MachineState *machine)
|
||||
{
|
||||
sun4m_hw_init(&sun4m_hwdefs[8], machine);
|
||||
}
|
||||
|
||||
static void ss5_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sun4m platform, SPARCstation 5";
|
||||
mc->init = ss5_init;
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->is_default = true;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
|
||||
mc->default_display = "tcx";
|
||||
mc->default_ram_id = "sun4m.ram";
|
||||
}
|
||||
|
||||
static const TypeInfo ss5_type = {
|
||||
.name = MACHINE_TYPE_NAME("SS-5"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = ss5_class_init,
|
||||
};
|
||||
|
||||
static void ss10_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sun4m platform, SPARCstation 10";
|
||||
mc->init = ss10_init;
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->max_cpus = 4;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
|
||||
mc->default_display = "tcx";
|
||||
mc->default_ram_id = "sun4m.ram";
|
||||
}
|
||||
|
||||
static const TypeInfo ss10_type = {
|
||||
.name = MACHINE_TYPE_NAME("SS-10"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = ss10_class_init,
|
||||
};
|
||||
|
||||
static void ss600mp_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sun4m platform, SPARCserver 600MP";
|
||||
mc->init = ss600mp_init;
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->max_cpus = 4;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
|
||||
mc->default_display = "tcx";
|
||||
mc->default_ram_id = "sun4m.ram";
|
||||
}
|
||||
|
||||
static const TypeInfo ss600mp_type = {
|
||||
.name = MACHINE_TYPE_NAME("SS-600MP"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = ss600mp_class_init,
|
||||
};
|
||||
|
||||
static void ss20_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sun4m platform, SPARCstation 20";
|
||||
mc->init = ss20_init;
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->max_cpus = 4;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
|
||||
mc->default_display = "tcx";
|
||||
mc->default_ram_id = "sun4m.ram";
|
||||
}
|
||||
|
||||
static const TypeInfo ss20_type = {
|
||||
.name = MACHINE_TYPE_NAME("SS-20"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = ss20_class_init,
|
||||
};
|
||||
|
||||
static void voyager_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sun4m platform, SPARCstation Voyager";
|
||||
mc->init = vger_init;
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
|
||||
mc->default_display = "tcx";
|
||||
mc->default_ram_id = "sun4m.ram";
|
||||
}
|
||||
|
||||
static const TypeInfo voyager_type = {
|
||||
.name = MACHINE_TYPE_NAME("Voyager"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = voyager_class_init,
|
||||
};
|
||||
|
||||
static void ss_lx_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sun4m platform, SPARCstation LX";
|
||||
mc->init = ss_lx_init;
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
|
||||
mc->default_display = "tcx";
|
||||
mc->default_ram_id = "sun4m.ram";
|
||||
}
|
||||
|
||||
static const TypeInfo ss_lx_type = {
|
||||
.name = MACHINE_TYPE_NAME("LX"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = ss_lx_class_init,
|
||||
};
|
||||
|
||||
static void ss4_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sun4m platform, SPARCstation 4";
|
||||
mc->init = ss4_init;
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
|
||||
mc->default_display = "tcx";
|
||||
mc->default_ram_id = "sun4m.ram";
|
||||
}
|
||||
|
||||
static const TypeInfo ss4_type = {
|
||||
.name = MACHINE_TYPE_NAME("SS-4"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = ss4_class_init,
|
||||
};
|
||||
|
||||
static void scls_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
|
||||
mc->desc = "Sun4m platform, SPARCClassic";
|
||||
mc->init = scls_init;
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
|
||||
mc->default_display = "tcx";
|
||||
mc->default_ram_id = "sun4m.ram";
|
||||
}
|
||||
|
||||
static const TypeInfo scls_type = {
|
||||
.name = MACHINE_TYPE_NAME("SPARCClassic"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = scls_class_init,
|
||||
};
|
||||
|
||||
static void sbook_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
MachineClass *mc = MACHINE_CLASS(oc);
|
||||
};
|
||||
|
||||
mc->desc = "Sun4m platform, SPARCbook";
|
||||
mc->init = sbook_init;
|
||||
mc->block_default_type = IF_SCSI;
|
||||
mc->default_boot_order = "c";
|
||||
mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
|
||||
mc->default_display = "tcx";
|
||||
mc->default_ram_id = "sun4m.ram";
|
||||
smc->hwdef = &sbook_hwdef;
|
||||
}
|
||||
|
||||
static const TypeInfo sbook_type = {
|
||||
.name = MACHINE_TYPE_NAME("SPARCbook"),
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_init = sbook_class_init,
|
||||
static const TypeInfo sun4m_machine_types[] = {
|
||||
{
|
||||
.name = MACHINE_TYPE_NAME("SS-5"),
|
||||
.parent = TYPE_SUN4M_MACHINE,
|
||||
.class_init = ss5_class_init,
|
||||
}, {
|
||||
.name = MACHINE_TYPE_NAME("SS-10"),
|
||||
.parent = TYPE_SUN4M_MACHINE,
|
||||
.class_init = ss10_class_init,
|
||||
}, {
|
||||
.name = MACHINE_TYPE_NAME("SS-600MP"),
|
||||
.parent = TYPE_SUN4M_MACHINE,
|
||||
.class_init = ss600mp_class_init,
|
||||
}, {
|
||||
.name = MACHINE_TYPE_NAME("SS-20"),
|
||||
.parent = TYPE_SUN4M_MACHINE,
|
||||
.class_init = ss20_class_init,
|
||||
}, {
|
||||
.name = MACHINE_TYPE_NAME("Voyager"),
|
||||
.parent = TYPE_SUN4M_MACHINE,
|
||||
.class_init = voyager_class_init,
|
||||
}, {
|
||||
.name = MACHINE_TYPE_NAME("LX"),
|
||||
.parent = TYPE_SUN4M_MACHINE,
|
||||
.class_init = ss_lx_class_init,
|
||||
}, {
|
||||
.name = MACHINE_TYPE_NAME("SS-4"),
|
||||
.parent = TYPE_SUN4M_MACHINE,
|
||||
.class_init = ss4_class_init,
|
||||
}, {
|
||||
.name = MACHINE_TYPE_NAME("SPARCClassic"),
|
||||
.parent = TYPE_SUN4M_MACHINE,
|
||||
.class_init = scls_class_init,
|
||||
}, {
|
||||
.name = MACHINE_TYPE_NAME("SPARCbook"),
|
||||
.parent = TYPE_SUN4M_MACHINE,
|
||||
.class_init = sbook_class_init,
|
||||
}, {
|
||||
.name = TYPE_SUN4M_MACHINE,
|
||||
.parent = TYPE_MACHINE,
|
||||
.class_size = sizeof(Sun4mMachineClass),
|
||||
.class_init = sun4m_machine_class_init,
|
||||
.abstract = true,
|
||||
}
|
||||
};
|
||||
|
||||
DEFINE_TYPES(sun4m_machine_types)
|
||||
|
||||
static void sun4m_register_types(void)
|
||||
{
|
||||
type_register_static(&idreg_info);
|
||||
type_register_static(&afx_info);
|
||||
type_register_static(&prom_info);
|
||||
type_register_static(&ram_info);
|
||||
|
||||
type_register_static(&ss5_type);
|
||||
type_register_static(&ss10_type);
|
||||
type_register_static(&ss600mp_type);
|
||||
type_register_static(&ss20_type);
|
||||
type_register_static(&voyager_type);
|
||||
type_register_static(&ss_lx_type);
|
||||
type_register_static(&ss4_type);
|
||||
type_register_static(&scls_type);
|
||||
type_register_static(&sbook_type);
|
||||
}
|
||||
|
||||
type_init(sun4m_register_types)
|
||||
|
@ -1,8 +1,6 @@
|
||||
# See docs/devel/tracing.txt for syntax documentation.
|
||||
|
||||
# sun4m.c
|
||||
sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
|
||||
sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
|
||||
sun4m_cpu_set_irq_raise(int level) "Raise CPU IRQ %d"
|
||||
sun4m_cpu_set_irq_lower(int level) "Lower CPU IRQ %d"
|
||||
|
||||
@ -19,3 +17,5 @@ sun4m_iommu_bad_addr(uint64_t addr) "bad addr 0x%"PRIx64
|
||||
# leon3.c
|
||||
leon3_set_irq(int intno) "Set CPU IRQ %d"
|
||||
leon3_reset_irq(int intno) "Reset CPU IRQ %d"
|
||||
int_helper_icache_freeze(void) "Instruction cache: freeze"
|
||||
int_helper_dcache_freeze(void) "Data cache: freeze"
|
||||
|
@ -26,7 +26,6 @@
|
||||
#include "qemu/osdep.h"
|
||||
#include "cpu.h"
|
||||
#include "hw/boards.h"
|
||||
#include "hw/char/serial.h"
|
||||
#include "hw/sparc/sparc64.h"
|
||||
#include "qemu/timer.h"
|
||||
#include "sysemu/reset.h"
|
||||
@ -35,68 +34,6 @@
|
||||
|
||||
#define TICK_MAX 0x7fffffffffffffffULL
|
||||
|
||||
void cpu_check_irqs(CPUSPARCState *env)
|
||||
{
|
||||
CPUState *cs;
|
||||
uint32_t pil = env->pil_in |
|
||||
(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
|
||||
|
||||
/* We should be holding the BQL before we mess with IRQs */
|
||||
g_assert(qemu_mutex_iothread_locked());
|
||||
|
||||
/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
|
||||
if (env->ivec_status & 0x20) {
|
||||
return;
|
||||
}
|
||||
cs = env_cpu(env);
|
||||
/* check if TM or SM in SOFTINT are set
|
||||
setting these also causes interrupt 14 */
|
||||
if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
|
||||
pil |= 1 << 14;
|
||||
}
|
||||
|
||||
/* The bit corresponding to psrpil is (1<< psrpil), the next bit
|
||||
is (2 << psrpil). */
|
||||
if (pil < (2 << env->psrpil)) {
|
||||
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
|
||||
trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
|
||||
env->interrupt_index = 0;
|
||||
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if (cpu_interrupts_enabled(env)) {
|
||||
|
||||
unsigned int i;
|
||||
|
||||
for (i = 15; i > env->psrpil; i--) {
|
||||
if (pil & (1 << i)) {
|
||||
int old_interrupt = env->interrupt_index;
|
||||
int new_interrupt = TT_EXTINT | i;
|
||||
|
||||
if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
|
||||
&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
|
||||
trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
|
||||
cpu_tsptr(env)->tt,
|
||||
new_interrupt);
|
||||
} else if (old_interrupt != new_interrupt) {
|
||||
env->interrupt_index = new_interrupt;
|
||||
trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
|
||||
new_interrupt);
|
||||
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
|
||||
trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
|
||||
env->interrupt_index);
|
||||
env->interrupt_index = 0;
|
||||
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
}
|
||||
|
||||
static void cpu_kick_irq(SPARCCPU *cpu)
|
||||
{
|
||||
CPUState *cs = CPU(cpu);
|
||||
|
@ -9,10 +9,6 @@ sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64"
|
||||
sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64
|
||||
|
||||
# sparc64.c
|
||||
sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)"
|
||||
sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x"
|
||||
sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x"
|
||||
sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x"
|
||||
sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d"
|
||||
sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d"
|
||||
sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled"
|
||||
|
@ -615,15 +615,9 @@ int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
|
||||
int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
|
||||
void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
|
||||
|
||||
/* int_helper.c */
|
||||
void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
|
||||
|
||||
/* sun4m.c, sun4u.c */
|
||||
void cpu_check_irqs(CPUSPARCState *env);
|
||||
|
||||
/* leon3.c */
|
||||
void leon3_irq_ack(void *irq_manager, int intno);
|
||||
|
||||
#if defined (TARGET_SPARC64)
|
||||
|
||||
static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
|
||||
|
@ -18,6 +18,7 @@
|
||||
*/
|
||||
|
||||
#include "qemu/osdep.h"
|
||||
#include "qemu/main-loop.h"
|
||||
#include "cpu.h"
|
||||
#include "trace.h"
|
||||
#include "exec/log.h"
|
||||
@ -64,6 +65,38 @@ static const char *excp_name_str(int32_t exception_index)
|
||||
return excp_names[exception_index];
|
||||
}
|
||||
|
||||
void cpu_check_irqs(CPUSPARCState *env)
|
||||
{
|
||||
CPUState *cs;
|
||||
|
||||
/* We should be holding the BQL before we mess with IRQs */
|
||||
g_assert(qemu_mutex_iothread_locked());
|
||||
|
||||
if (env->pil_in && (env->interrupt_index == 0 ||
|
||||
(env->interrupt_index & ~15) == TT_EXTINT)) {
|
||||
unsigned int i;
|
||||
|
||||
for (i = 15; i > 0; i--) {
|
||||
if (env->pil_in & (1 << i)) {
|
||||
int old_interrupt = env->interrupt_index;
|
||||
|
||||
env->interrupt_index = TT_EXTINT | i;
|
||||
if (old_interrupt != env->interrupt_index) {
|
||||
cs = env_cpu(env);
|
||||
trace_sun4m_cpu_interrupt(i);
|
||||
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
|
||||
cs = env_cpu(env);
|
||||
trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
|
||||
env->interrupt_index = 0;
|
||||
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
}
|
||||
|
||||
void sparc_cpu_do_interrupt(CPUState *cs)
|
||||
{
|
||||
SPARCCPU *cpu = SPARC_CPU(cs);
|
||||
@ -136,40 +169,3 @@ void sparc_cpu_do_interrupt(CPUState *cs)
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
static void leon3_cache_control_int(CPUSPARCState *env)
|
||||
{
|
||||
uint32_t state = 0;
|
||||
|
||||
if (env->cache_control & CACHE_CTRL_IF) {
|
||||
/* Instruction cache state */
|
||||
state = env->cache_control & CACHE_STATE_MASK;
|
||||
if (state == CACHE_ENABLED) {
|
||||
state = CACHE_FROZEN;
|
||||
trace_int_helper_icache_freeze();
|
||||
}
|
||||
|
||||
env->cache_control &= ~CACHE_STATE_MASK;
|
||||
env->cache_control |= state;
|
||||
}
|
||||
|
||||
if (env->cache_control & CACHE_CTRL_DF) {
|
||||
/* Data cache state */
|
||||
state = (env->cache_control >> 2) & CACHE_STATE_MASK;
|
||||
if (state == CACHE_ENABLED) {
|
||||
state = CACHE_FROZEN;
|
||||
trace_int_helper_dcache_freeze();
|
||||
}
|
||||
|
||||
env->cache_control &= ~(CACHE_STATE_MASK << 2);
|
||||
env->cache_control |= (state << 2);
|
||||
}
|
||||
}
|
||||
|
||||
void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno)
|
||||
{
|
||||
leon3_irq_ack(irq_manager, intno);
|
||||
leon3_cache_control_int(env);
|
||||
}
|
||||
#endif
|
||||
|
@ -62,6 +62,72 @@ static const char * const excp_names[0x80] = {
|
||||
};
|
||||
#endif
|
||||
|
||||
void cpu_check_irqs(CPUSPARCState *env)
|
||||
{
|
||||
CPUState *cs;
|
||||
uint32_t pil = env->pil_in |
|
||||
(env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
|
||||
|
||||
/* We should be holding the BQL before we mess with IRQs */
|
||||
g_assert(qemu_mutex_iothread_locked());
|
||||
|
||||
/* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
|
||||
if (env->ivec_status & 0x20) {
|
||||
return;
|
||||
}
|
||||
cs = env_cpu(env);
|
||||
/*
|
||||
* check if TM or SM in SOFTINT are set
|
||||
* setting these also causes interrupt 14
|
||||
*/
|
||||
if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
|
||||
pil |= 1 << 14;
|
||||
}
|
||||
|
||||
/*
|
||||
* The bit corresponding to psrpil is (1<< psrpil),
|
||||
* the next bit is (2 << psrpil).
|
||||
*/
|
||||
if (pil < (2 << env->psrpil)) {
|
||||
if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
|
||||
trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);
|
||||
env->interrupt_index = 0;
|
||||
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
if (cpu_interrupts_enabled(env)) {
|
||||
|
||||
unsigned int i;
|
||||
|
||||
for (i = 15; i > env->psrpil; i--) {
|
||||
if (pil & (1 << i)) {
|
||||
int old_interrupt = env->interrupt_index;
|
||||
int new_interrupt = TT_EXTINT | i;
|
||||
|
||||
if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt
|
||||
&& ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) {
|
||||
trace_sparc64_cpu_check_irqs_noset_irq(env->tl,
|
||||
cpu_tsptr(env)->tt,
|
||||
new_interrupt);
|
||||
} else if (old_interrupt != new_interrupt) {
|
||||
env->interrupt_index = new_interrupt;
|
||||
trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt,
|
||||
new_interrupt);
|
||||
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
|
||||
trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint,
|
||||
env->interrupt_index);
|
||||
env->interrupt_index = 0;
|
||||
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
||||
}
|
||||
}
|
||||
|
||||
void sparc_cpu_do_interrupt(CPUState *cs)
|
||||
{
|
||||
SPARCCPU *cpu = SPARC_CPU(cs);
|
||||
|
@ -10,14 +10,18 @@ mmu_helper_get_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, u
|
||||
mmu_helper_get_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t address) "tl=%d mmu_idx=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64" address=0x%"PRIx64
|
||||
mmu_helper_mmu_fault(uint64_t address, uint64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at 0x%"PRIx64" -> 0x%"PRIx64", mmu_idx=%d tl=%d primary context=0x%"PRIx64" secondary context=0x%"PRIx64
|
||||
|
||||
# int32_helper.c
|
||||
sun4m_cpu_interrupt(unsigned int level) "Set CPU IRQ %d"
|
||||
sun4m_cpu_reset_interrupt(unsigned int level) "Reset CPU IRQ %d"
|
||||
|
||||
# int64_helper.c
|
||||
int_helper_set_softint(uint32_t softint) "new 0x%08x"
|
||||
int_helper_clear_softint(uint32_t softint) "new 0x%08x"
|
||||
int_helper_write_softint(uint32_t softint) "new 0x%08x"
|
||||
|
||||
# int32_helper.c
|
||||
int_helper_icache_freeze(void) "Instruction cache: freeze"
|
||||
int_helper_dcache_freeze(void) "Data cache: freeze"
|
||||
sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)"
|
||||
sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x"
|
||||
sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x"
|
||||
sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x"
|
||||
|
||||
# win_helper.c
|
||||
win_helper_gregset_error(uint32_t pstate) "ERROR in get_gregset: active pstate bits=0x%x"
|
||||
|
Loading…
Reference in New Issue
Block a user