target-arm: Add GIC phandle to VirtBoardInfo
Instead of passing the GIC phandle around between functions, add it to the VirtBoardInfo just like we do for the clock_phandle. We are about to add the v2m phandle as well, and it's easier not having to pass around a bunch of phandles, return multiple values from functions, etc. Reviewed-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -69,6 +69,7 @@ typedef struct VirtBoardInfo {
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void *fdt;
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int fdt_size;
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uint32_t clock_phandle;
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uint32_t gic_phandle;
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} VirtBoardInfo;
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typedef struct {
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@ -299,12 +300,11 @@ static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
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}
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}
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static uint32_t fdt_add_gic_node(const VirtBoardInfo *vbi)
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static void fdt_add_gic_node(VirtBoardInfo *vbi)
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{
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uint32_t gic_phandle;
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gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
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qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", gic_phandle);
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vbi->gic_phandle = qemu_fdt_alloc_phandle(vbi->fdt);
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qemu_fdt_setprop_cell(vbi->fdt, "/", "interrupt-parent", vbi->gic_phandle);
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qemu_fdt_add_subnode(vbi->fdt, "/intc");
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/* 'cortex-a15-gic' means 'GIC v2' */
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@ -317,12 +317,10 @@ static uint32_t fdt_add_gic_node(const VirtBoardInfo *vbi)
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2, vbi->memmap[VIRT_GIC_DIST].size,
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2, vbi->memmap[VIRT_GIC_CPU].base,
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2, vbi->memmap[VIRT_GIC_CPU].size);
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qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", gic_phandle);
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return gic_phandle;
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qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle);
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}
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static uint32_t create_gic(const VirtBoardInfo *vbi, qemu_irq *pic)
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static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic)
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{
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/* We create a standalone GIC v2 */
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DeviceState *gicdev;
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@ -371,7 +369,7 @@ static uint32_t create_gic(const VirtBoardInfo *vbi, qemu_irq *pic)
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pic[i] = qdev_get_gpio_in(gicdev, i);
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}
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return fdt_add_gic_node(vbi);
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fdt_add_gic_node(vbi);
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}
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static void create_uart(const VirtBoardInfo *vbi, qemu_irq *pic)
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@ -618,8 +616,7 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle,
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0x7 /* PCI irq */);
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}
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static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
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uint32_t gic_phandle)
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static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic)
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{
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hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base;
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hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size;
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@ -685,7 +682,7 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
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2, base_mmio, 2, size_mmio);
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qemu_fdt_setprop_cell(vbi->fdt, nodename, "#interrupt-cells", 1);
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create_pcie_irq_map(vbi, gic_phandle, irq, nodename);
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create_pcie_irq_map(vbi, vbi->gic_phandle, irq, nodename);
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g_free(nodename);
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}
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@ -717,7 +714,6 @@ static void machvirt_init(MachineState *machine)
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VirtBoardInfo *vbi;
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VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
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VirtGuestInfo *guest_info = &guest_info_state->info;
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uint32_t gic_phandle;
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char **cpustr;
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if (!cpu_model) {
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@ -794,13 +790,13 @@ static void machvirt_init(MachineState *machine)
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create_flash(vbi);
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gic_phandle = create_gic(vbi, pic);
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create_gic(vbi, pic);
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create_uart(vbi, pic);
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create_rtc(vbi, pic);
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create_pcie(vbi, pic, gic_phandle);
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create_pcie(vbi, pic);
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/* Create mmio transports, so the user can create virtio backends
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* (which will be automatically plugged in to the transports). If
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