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Misc fixes for 8.2

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* buildsys: Invoke bash via 'env' (Samuel)
 
 * doc: Fix example in s390-cpu-topology.rst (Zhao)
 
 * HW: Fix AVR ATMega reset stack (Gihun) and VT82C686 IRQ routing (Zoltan)
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Merge tag 'misc-next-20231128' of https://github.com/philmd/qemu into staging

Misc fixes for 8.2

* buildsys: Invoke bash via 'env' (Samuel)

* doc: Fix example in s390-cpu-topology.rst (Zhao)

* HW: Fix AVR ATMega reset stack (Gihun) and VT82C686 IRQ routing (Zoltan)

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# gpg: Signature made Tue 28 Nov 2023 08:36:05 EST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
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# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'misc-next-20231128' of https://github.com/philmd/qemu:
  docs/s390: Fix wrong command example in s390-cpu-topology.rst
  hw/avr/atmega: Fix wrong initial value of stack pointer
  hw/audio/via-ac97: Route interrupts using via_isa_set_irq()
  hw/isa/vt82c686: Route PIRQ inputs using via_isa_set_irq()
  hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts
  hw/isa/vt82c686: Bring back via_isa_set_irq()
  target/hexagon/idef-parser/prepare: use env to invoke bash

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-11-28 15:36:42 -05:00
commit 745c2911cc
9 changed files with 87 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
docs/devel/s390-cpu-topology.rst
View File

@ -15,7 +15,7 @@ have default values:
-smp 1,drawers=3,books=3,sockets=2,cores=2,maxcpus=36 \
-device z14-s390x-cpu,core-id=19,entitlement=high \
-device z14-s390x-cpu,core-id=11,entitlement=low \
-device z14-s390x-cpu,core-id=112,entitlement=high \
-device z14-s390x-cpu,core-id=12,entitlement=high \
...
Additions to query-cpus-fast
@ -78,7 +78,7 @@ modifiers for all configured vCPUs.
"dedicated": true,
"thread-id": 537005,
"props": {
"core-id": 112,
"core-id": 12,
"socket-id": 0,
"drawer-id": 3,
"book-id": 2
@ -86,7 +86,7 @@ modifiers for all configured vCPUs.
"cpu-state": "operating",
"entitlement": "high",
"qom-path": "/machine/peripheral-anon/device[2]",
"cpu-index": 112,
"cpu-index": 12,
"target": "s390x"
}
]

8
hw/audio/via-ac97.c
View File

@ -211,14 +211,14 @@ static void out_cb(void *opaque, int avail)
AUD_set_active_out(s->vo, 0);
}
if (c->type & STAT_EOL) {
pci_set_irq(&s->dev, 1);
via_isa_set_irq(&s->dev, 0, 1);
}
}
if (CLEN_IS_FLAG(c)) {
c->stat |= STAT_FLAG;
c->stat |= STAT_PAUSED;
if (c->type & STAT_FLAG) {
pci_set_irq(&s->dev, 1);
via_isa_set_irq(&s->dev, 0, 1);
}
}
if (CLEN_IS_STOP(c)) {
@ -305,13 +305,13 @@ static void sgd_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
if (val & STAT_EOL) {
s->aur.stat &= ~(STAT_EOL | STAT_PAUSED);
if (s->aur.type & STAT_EOL) {
pci_set_irq(&s->dev, 0);
via_isa_set_irq(&s->dev, 0, 0);
}
}
if (val & STAT_FLAG) {
s->aur.stat &= ~(STAT_FLAG | STAT_PAUSED);
if (s->aur.type & STAT_FLAG) {
pci_set_irq(&s->dev, 0);
via_isa_set_irq(&s->dev, 0, 0);
}
}
break;

4
hw/avr/atmega.c
View File

@ -233,6 +233,10 @@ static void atmega_realize(DeviceState *dev, Error **errp)
/* CPU */
object_initialize_child(OBJECT(dev), "cpu", &s->cpu, mc->cpu_type);
object_property_set_uint(OBJECT(&s->cpu), "init-sp",
mc->io_size + mc->sram_size - 1, &error_abort);
qdev_realize(DEVICE(&s->cpu), NULL, &error_abort);
cpudev = DEVICE(&s->cpu);

79
hw/isa/vt82c686.c
View File

@ -549,6 +549,7 @@ struct ViaISAState {
PCIDevice dev;
qemu_irq cpu_intr;
qemu_irq *isa_irqs_in;
uint16_t irq_state[ISA_NUM_IRQS];
ViaSuperIOState via_sio;
MC146818RtcState rtc;
PCIIDEState ide;
@ -592,15 +593,9 @@ static const TypeInfo via_isa_info = {
},
};
static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
static int via_isa_get_pci_irq(const ViaISAState *s, int pin)
{
ViaISAState *s = opaque;
qemu_set_irq(s->cpu_intr, level);
}
static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num)
{
switch (irq_num) {
switch (pin) {
case 0:
return s->dev.config[0x55] >> 4;
case 1:
@ -613,29 +608,60 @@ static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num)
return 0;
}
static void via_isa_set_pci_irq(void *opaque, int irq_num, int level)
void via_isa_set_irq(PCIDevice *d, int pin, int level)
{
ViaISAState *s = opaque;
PCIBus *bus = pci_get_bus(&s->dev);
int i, pic_level, pic_irq = via_isa_get_pci_irq(s, irq_num);
ViaISAState *s = VIA_ISA(pci_get_function_0(d));
uint8_t irq = d->config[PCI_INTERRUPT_LINE], max_irq = 15;
int f = PCI_FUNC(d->devfn);
uint16_t mask = BIT(f);
/* IRQ 0: disabled, IRQ 2,8,13: reserved */
if (!pic_irq) {
switch (f) {
case 0: /* PIRQ/PINT inputs */
irq = via_isa_get_pci_irq(s, pin);
f = 8 + pin; /* Use function 8-11 for PCI interrupt inputs */
break;
case 2: /* USB ports 0-1 */
case 3: /* USB ports 2-3 */
case 5: /* AC97 audio */
max_irq = 14;
break;
}
/* Keep track of the state of all sources */
if (level) {
s->irq_state[0] |= mask;
} else {
s->irq_state[0] &= ~mask;
}
if (irq == 0 || irq == 0xff) {
return; /* disabled */
}
if (unlikely(irq > max_irq || irq == 2)) {
qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing %d for %d",
irq, f);
return;
}
if (unlikely(pic_irq == 2 || pic_irq == 8 || pic_irq == 13)) {
qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing");
/* Record source state at mapped IRQ */
if (level) {
s->irq_state[irq] |= mask;
} else {
s->irq_state[irq] &= ~mask;
}
/* Make sure there are no stuck bits if mapping has changed */
s->irq_state[irq] &= s->irq_state[0];
/* ISA IRQ level is the OR of all sources routed to it */
qemu_set_irq(s->isa_irqs_in[irq], !!s->irq_state[irq]);
}
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0;
for (i = 0; i < PCI_NUM_PINS; i++) {
if (pic_irq == via_isa_get_pci_irq(s, i)) {
pic_level |= pci_bus_get_irq_level(bus, i);
}
}
/* Now we change the pic irq level according to the via irq mappings. */
qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level);
static void via_isa_pirq(void *opaque, int pin, int level)
{
via_isa_set_irq(opaque, pin, level);
}
static void via_isa_request_i8259_irq(void *opaque, int irq, int level)
{
ViaISAState *s = opaque;
qemu_set_irq(s->cpu_intr, level);
}
static void via_isa_realize(PCIDevice *d, Error **errp)
@ -648,6 +674,7 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
int i;
qdev_init_gpio_out(dev, &s->cpu_intr, 1);
qdev_init_gpio_in_named(dev, via_isa_pirq, "pirq", PCI_NUM_PINS);
isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1);
isa_bus = isa_bus_new(dev, pci_address_space(d), pci_address_space_io(d),
errp);
@ -661,8 +688,6 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
i8254_pit_init(isa_bus, 0x40, 0, NULL);
i8257_dma_init(isa_bus, 0);
qdev_init_gpio_in_named(dev, via_isa_set_pci_irq, "pirq", PCI_NUM_PINS);
/* RTC */
qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {

9
hw/usb/vt82c686-uhci-pci.c
View File

@ -1,7 +1,14 @@
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/isa/vt82c686.h"
#include "hcd-uhci.h"
static void uhci_isa_set_irq(void *opaque, int irq_num, int level)
{
UHCIState *s = opaque;
via_isa_set_irq(&s->dev, 0, level);
}
static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp)
{
UHCIState *s = UHCI(dev);
@ -15,6 +22,8 @@ static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp)
pci_set_long(pci_conf + 0xc0, 0x00002000);
usb_uhci_common_realize(dev, errp);
object_unref(s->irq);
s->irq = qemu_allocate_irq(uhci_isa_set_irq, s, 0);
}
static UHCIInfo uhci_info[] = {

2
include/hw/isa/vt82c686.h
View File

@ -34,4 +34,6 @@ struct ViaAC97State {
uint32_t ac97_cmd;
};
void via_isa_set_irq(PCIDevice *d, int n, int level);
#endif

10
target/avr/cpu.c
View File

@ -25,6 +25,7 @@
#include "cpu.h"
#include "disas/dis-asm.h"
#include "tcg/debug-assert.h"
#include "hw/qdev-properties.h"
static void avr_cpu_set_pc(CPUState *cs, vaddr value)
{
@ -95,7 +96,7 @@ static void avr_cpu_reset_hold(Object *obj)
env->rampY = 0;
env->rampZ = 0;
env->eind = 0;
env->sp = 0;
env->sp = cpu->init_sp;
env->skip = 0;
@ -152,6 +153,11 @@ static void avr_cpu_initfn(Object *obj)
sizeof(cpu->env.intsrc) * 8);
}
static Property avr_cpu_properties[] = {
DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0),
DEFINE_PROP_END_OF_LIST()
};
static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
@ -228,6 +234,8 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize);
device_class_set_props(dc, avr_cpu_properties);
resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL,
&mcc->parent_phases);

3
target/avr/cpu.h
View File

@ -145,6 +145,9 @@ struct ArchCPU {
CPUState parent_obj;
CPUAVRState env;
/* Initial value of stack pointer */
uint32_t init_sp;
};
/**

2
target/hexagon/idef-parser/prepare
View File

@ -1,4 +1,4 @@
#!/bin/bash
#!/usr/bin/env bash
#
# Copyright(c) 2019-2021 rev.ng Labs Srl. All Rights Reserved.