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target/riscv: Move misa_mxl_max to class

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misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240203-riscv-v11-2-a23f4848a628@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Akihiko Odaki 2024-02-03 19:11:09 +09:00 committed by Alistair Francis
parent 0e350c1ada
commit 742cc269c7
8 changed files with 112 additions and 99 deletions
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3
hw/riscv/boot.c
View File

@ -36,7 +36,8 @@
bool riscv_is_32bit(RISCVHartArrayState *harts) bool riscv_is_32bit(RISCVHartArrayState *harts)
{ {
return harts->harts[0].env.misa_mxl_max == MXL_RV32; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(&harts->harts[0]);
return mcc->misa_mxl_max == MXL_RV32;
} }
/* /*

160
target/riscv/cpu.c
View File

@ -301,9 +301,8 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
} }
} }
void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
{ {
env->misa_mxl_max = env->misa_mxl = mxl;
env->misa_ext_mask = env->misa_ext = ext; env->misa_ext_mask = env->misa_ext = ext;
} }
@ -416,11 +415,7 @@ static void riscv_any_cpu_init(Object *obj)
{ {
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
#if defined(TARGET_RISCV32) riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#elif defined(TARGET_RISCV64)
riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#endif
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), set_satp_mode_max_supported(RISCV_CPU(obj),
@ -441,19 +436,17 @@ static void riscv_max_cpu_init(Object *obj)
{ {
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
RISCVMXL mlx = MXL_RV64;
cpu->cfg.mmu = true; cpu->cfg.mmu = true;
cpu->cfg.pmp = true; cpu->cfg.pmp = true;
#ifdef TARGET_RISCV32
mlx = MXL_RV32;
#endif
riscv_cpu_set_misa(env, mlx, 0);
env->priv_ver = PRIV_VERSION_LATEST; env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ? #ifdef TARGET_RISCV32
VM_1_10_SV32 : VM_1_10_SV57); set_satp_mode_max_supported(cpu, VM_1_10_SV32);
#else
set_satp_mode_max_supported(cpu, VM_1_10_SV57);
#endif
#endif #endif
} }
@ -466,8 +459,6 @@ static void rv64_base_cpu_init(Object *obj)
cpu->cfg.mmu = true; cpu->cfg.mmu = true;
cpu->cfg.pmp = true; cpu->cfg.pmp = true;
/* We set this in the realise function */
riscv_cpu_set_misa(env, MXL_RV64, 0);
/* Set latest version of privileged specification */ /* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST; env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -479,8 +470,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
{ {
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
riscv_cpu_set_misa(env, MXL_RV64, riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0; env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
@ -498,7 +488,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0; env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE); set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@ -515,7 +505,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_11_0; env->priv_ver = PRIV_VERSION_1_11_0;
cpu->cfg.ext_zfa = true; cpu->cfg.ext_zfa = true;
@ -546,7 +536,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH);
env->priv_ver = PRIV_VERSION_1_12_0; env->priv_ver = PRIV_VERSION_1_12_0;
/* Enable ISA extensions */ /* Enable ISA extensions */
@ -596,8 +586,6 @@ static void rv128_base_cpu_init(Object *obj)
cpu->cfg.mmu = true; cpu->cfg.mmu = true;
cpu->cfg.pmp = true; cpu->cfg.pmp = true;
/* We set this in the realise function */
riscv_cpu_set_misa(env, MXL_RV128, 0);
/* Set latest version of privileged specification */ /* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST; env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -608,7 +596,7 @@ static void rv128_base_cpu_init(Object *obj)
static void rv64i_bare_cpu_init(Object *obj) static void rv64i_bare_cpu_init(Object *obj)
{ {
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
riscv_cpu_set_misa(env, MXL_RV64, RVI); riscv_cpu_set_misa_ext(env, RVI);
/* Remove the defaults from the parent class */ /* Remove the defaults from the parent class */
RISCV_CPU(obj)->cfg.ext_zicntr = false; RISCV_CPU(obj)->cfg.ext_zicntr = false;
@ -635,8 +623,6 @@ static void rv32_base_cpu_init(Object *obj)
cpu->cfg.mmu = true; cpu->cfg.mmu = true;
cpu->cfg.pmp = true; cpu->cfg.pmp = true;
/* We set this in the realise function */
riscv_cpu_set_misa(env, MXL_RV32, 0);
/* Set latest version of privileged specification */ /* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST; env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
@ -648,8 +634,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
{ {
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
riscv_cpu_set_misa(env, MXL_RV32, riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0; env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
@ -667,7 +652,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0; env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE); set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@ -684,7 +669,7 @@ static void rv32_ibex_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_12_0; env->priv_ver = PRIV_VERSION_1_12_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE); set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@ -701,7 +686,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env; CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0; env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE); set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@ -926,7 +911,7 @@ static void riscv_cpu_reset_hold(Object *obj)
mcc->parent_phases.hold(obj); mcc->parent_phases.hold(obj);
} }
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
env->misa_mxl = env->misa_mxl_max; env->misa_mxl = mcc->misa_mxl_max;
env->priv = PRV_M; env->priv = PRV_M;
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
if (env->misa_mxl > MXL_RV32) { if (env->misa_mxl > MXL_RV32) {
@ -1303,7 +1288,11 @@ static void riscv_cpu_post_init(Object *obj)
static void riscv_cpu_init(Object *obj) static void riscv_cpu_init(Object *obj)
{ {
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
env->misa_mxl = mcc->misa_mxl_max;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
@ -2281,7 +2270,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops = {
}; };
#endif #endif
static void riscv_cpu_class_init(ObjectClass *c, void *data) static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
{ {
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c);
@ -2315,6 +2304,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
device_class_set_props(dc, riscv_cpu_properties); device_class_set_props(dc, riscv_cpu_properties);
} }
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
}
static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
int max_str_len) int max_str_len)
{ {
@ -2351,39 +2347,49 @@ char *riscv_isa_string(RISCVCPU *cpu)
return isa_str; return isa_str;
} }
#define DEFINE_CPU(type_name, initfn) \ #define DEFINE_CPU(type_name, misa_mxl_max, initfn) \
{ \ { \
.name = type_name, \ .name = (type_name), \
.parent = TYPE_RISCV_CPU, \ .parent = TYPE_RISCV_CPU, \
.instance_init = initfn \ .instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
.class_data = (void *)(misa_mxl_max) \
} }
#define DEFINE_DYNAMIC_CPU(type_name, initfn) \ #define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \
{ \ { \
.name = type_name, \ .name = (type_name), \
.parent = TYPE_RISCV_DYNAMIC_CPU, \ .parent = TYPE_RISCV_DYNAMIC_CPU, \
.instance_init = initfn \ .instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
.class_data = (void *)(misa_mxl_max) \
} }
#define DEFINE_VENDOR_CPU(type_name, initfn) \ #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \
{ \ { \
.name = type_name, \ .name = (type_name), \
.parent = TYPE_RISCV_VENDOR_CPU, \ .parent = TYPE_RISCV_VENDOR_CPU, \
.instance_init = initfn \ .instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
.class_data = (void *)(misa_mxl_max) \
} }
#define DEFINE_BARE_CPU(type_name, initfn) \ #define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \
{ \ { \
.name = type_name, \ .name = (type_name), \
.parent = TYPE_RISCV_BARE_CPU, \ .parent = TYPE_RISCV_BARE_CPU, \
.instance_init = initfn \ .instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
.class_data = (void *)(misa_mxl_max) \
} }
#define DEFINE_PROFILE_CPU(type_name, initfn) \ #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \
{ \ { \
.name = type_name, \ .name = (type_name), \
.parent = TYPE_RISCV_BARE_CPU, \ .parent = TYPE_RISCV_BARE_CPU, \
.instance_init = initfn \ .instance_init = (initfn), \
.class_init = riscv_cpu_class_init, \
.class_data = (void *)(misa_mxl_max) \
} }
static const TypeInfo riscv_cpu_type_infos[] = { static const TypeInfo riscv_cpu_type_infos[] = {
@ -2396,7 +2402,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.instance_post_init = riscv_cpu_post_init, .instance_post_init = riscv_cpu_post_init,
.abstract = true, .abstract = true,
.class_size = sizeof(RISCVCPUClass), .class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_class_init, .class_init = riscv_cpu_common_class_init,
}, },
{ {
.name = TYPE_RISCV_DYNAMIC_CPU, .name = TYPE_RISCV_DYNAMIC_CPU,
@ -2413,25 +2419,27 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.parent = TYPE_RISCV_CPU, .parent = TYPE_RISCV_CPU,
.abstract = true, .abstract = true,
}, },
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init),
#if defined(TARGET_RISCV32) #if defined(TARGET_RISCV32)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
#elif defined(TARGET_RISCV64) #elif defined(TARGET_RISCV64)
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),
DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init),
DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init),
DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init), DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init),
DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init),
#endif #endif
}; };

4
target/riscv/cpu.h
View File

@ -189,7 +189,6 @@ struct CPUArchState {
/* RISCVMXL, but uint32_t for vmstate migration */ /* RISCVMXL, but uint32_t for vmstate migration */
uint32_t misa_mxl; /* current mxl */ uint32_t misa_mxl; /* current mxl */
uint32_t misa_mxl_max; /* max mxl for this cpu */
uint32_t misa_ext; /* current extensions */ uint32_t misa_ext; /* current extensions */
uint32_t misa_ext_mask; /* max ext for this cpu */ uint32_t misa_ext_mask; /* max ext for this cpu */
uint32_t xl; /* current xlen */ uint32_t xl; /* current xlen */
@ -471,6 +470,7 @@ struct RISCVCPUClass {
DeviceRealize parent_realize; DeviceRealize parent_realize;
ResettablePhases parent_phases; ResettablePhases parent_phases;
uint32_t misa_mxl_max; /* max mxl for this cpu */
}; };
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
@ -781,7 +781,7 @@ enum riscv_pmu_event_idx {
/* used by tcg/tcg-cpu.c*/ /* used by tcg/tcg-cpu.c*/
void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext);
bool riscv_cpu_is_vendor(Object *cpu_obj); bool riscv_cpu_is_vendor(Object *cpu_obj);
typedef struct RISCVCPUMultiExtConfig { typedef struct RISCVCPUMultiExtConfig {

12
target/riscv/gdbstub.c
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@ -49,6 +49,7 @@ static const struct TypeSize vec_lanes[] = {
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{ {
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
target_ulong tmp; target_ulong tmp;
@ -61,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0; return 0;
} }
switch (env->misa_mxl_max) { switch (mcc->misa_mxl_max) {
case MXL_RV32: case MXL_RV32:
return gdb_get_reg32(mem_buf, tmp); return gdb_get_reg32(mem_buf, tmp);
case MXL_RV64: case MXL_RV64:
@ -75,12 +76,13 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{ {
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
int length = 0; int length = 0;
target_ulong tmp; target_ulong tmp;
switch (env->misa_mxl_max) { switch (mcc->misa_mxl_max) {
case MXL_RV32: case MXL_RV32:
tmp = (int32_t)ldl_p(mem_buf); tmp = (int32_t)ldl_p(mem_buf);
length = 4; length = 4;
@ -214,11 +216,12 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
{ {
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
GString *s = g_string_new(NULL); GString *s = g_string_new(NULL);
riscv_csr_predicate_fn predicate; riscv_csr_predicate_fn predicate;
int bitsize = 16 << env->misa_mxl_max; int bitsize = 16 << mcc->misa_mxl_max;
int i; int i;
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
@ -310,6 +313,7 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg)
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{ {
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
if (env->misa_ext & RVD) { if (env->misa_ext & RVD) {
@ -326,7 +330,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
ricsv_gen_dynamic_vector_xml(cs, base_reg), ricsv_gen_dynamic_vector_xml(cs, base_reg),
"riscv-vector.xml", 0); "riscv-vector.xml", 0);
} }
switch (env->misa_mxl_max) { switch (mcc->misa_mxl_max) {
case MXL_RV32: case MXL_RV32:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual, riscv_gdb_set_virtual,

10
target/riscv/kvm/kvm-cpu.c
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@ -1769,14 +1769,14 @@ static void kvm_cpu_accel_register_types(void)
} }
type_init(kvm_cpu_accel_register_types); type_init(kvm_cpu_accel_register_types);
static void riscv_host_cpu_init(Object *obj) static void riscv_host_cpu_class_init(ObjectClass *c, void *data)
{ {
CPURISCVState *env = &RISCV_CPU(obj)->env; RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
#if defined(TARGET_RISCV32) #if defined(TARGET_RISCV32)
env->misa_mxl_max = env->misa_mxl = MXL_RV32; mcc->misa_mxl_max = MXL_RV32;
#elif defined(TARGET_RISCV64) #elif defined(TARGET_RISCV64)
env->misa_mxl_max = env->misa_mxl = MXL_RV64; mcc->misa_mxl_max = MXL_RV64;
#endif #endif
} }
@ -1784,7 +1784,7 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = {
{ {
.name = TYPE_RISCV_CPU_HOST, .name = TYPE_RISCV_CPU_HOST,
.parent = TYPE_RISCV_CPU, .parent = TYPE_RISCV_CPU,
.instance_init = riscv_host_cpu_init, .class_init = riscv_host_cpu_class_init,
} }
}; };

7
target/riscv/machine.c
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@ -178,10 +178,9 @@ static const VMStateDescription vmstate_pointermasking = {
static bool rv128_needed(void *opaque) static bool rv128_needed(void *opaque)
{ {
RISCVCPU *cpu = opaque; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(opaque);
CPURISCVState *env = &cpu->env;
return env->misa_mxl_max == MXL_RV128; return mcc->misa_mxl_max == MXL_RV128;
} }
static const VMStateDescription vmstate_rv128 = { static const VMStateDescription vmstate_rv128 = {
@ -372,7 +371,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.vext_ver, RISCVCPU), VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
VMSTATE_UINT32(env.misa_mxl, RISCVCPU), VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
VMSTATE_UINT32(env.misa_ext, RISCVCPU), VMSTATE_UINT32(env.misa_ext, RISCVCPU),
VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), VMSTATE_UNUSED(4),
VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU),
VMSTATE_BOOL(env.virt_enabled, RISCVCPU), VMSTATE_BOOL(env.virt_enabled, RISCVCPU),

12
target/riscv/tcg/tcg-cpu.c
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@ -272,10 +272,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)
{ {
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
CPUClass *cc = CPU_CLASS(mcc); CPUClass *cc = CPU_CLASS(mcc);
CPURISCVState *env = &cpu->env;
/* Validate that MISA_MXL is set properly. */ /* Validate that MISA_MXL is set properly. */
switch (env->misa_mxl_max) { switch (mcc->misa_mxl_max) {
#ifdef TARGET_RISCV64 #ifdef TARGET_RISCV64
case MXL_RV64: case MXL_RV64:
case MXL_RV128: case MXL_RV128:
@ -426,6 +425,7 @@ static void riscv_cpu_validate_b(RISCVCPU *cpu)
*/ */
void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
{ {
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
Error *local_err = NULL; Error *local_err = NULL;
@ -592,7 +592,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
} }
} }
@ -600,7 +600,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
/* zca, zcd and zcf has a PRIV 1.12.0 restriction */ /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
} }
if (riscv_has_ext(env, RVD)) { if (riscv_has_ext(env, RVD)) {
@ -608,7 +608,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
} }
} }
if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
error_setg(errp, "Zcf extension is only relevant to RV32"); error_setg(errp, "Zcf extension is only relevant to RV32");
return; return;
} }
@ -1307,7 +1307,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
const RISCVCPUMultiExtConfig *prop; const RISCVCPUMultiExtConfig *prop;
/* Enable RVG, RVJ and RVV that are disabled by default */ /* Enable RVG, RVJ and RVV that are disabled by default */
riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
isa_ext_update_enabled(cpu, prop->offset, true); isa_ext_update_enabled(cpu, prop->offset, true);

3
target/riscv/translate.c
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@ -1168,6 +1168,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{ {
DisasContext *ctx = container_of(dcbase, DisasContext, base); DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cpu_env(cs); CPURISCVState *env = cpu_env(cs);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
uint32_t tb_flags = ctx->base.tb->flags; uint32_t tb_flags = ctx->base.tb->flags;
@ -1189,7 +1190,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
ctx->misa_mxl_max = env->misa_mxl_max; ctx->misa_mxl_max = mcc->misa_mxl_max;
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs; ctx->cs = cs;