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target/i386: fix implementation of ICEBP

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ICEBP generates a trap-like exception, while gen_exception() produces
a fault.  Resurrect gen_update_eip_next() to implement the desired
semantics.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2024-05-29 13:17:27 +02:00
parent 69cb498c56
commit 73fb7b3c49
5 changed files with 49 additions and 2 deletions
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1
target/i386/helper.h
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@ -56,6 +56,7 @@ DEF_HELPER_2(sysret, void, env, int)
DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int)
DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int)
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int)
DEF_HELPER_FLAGS_1(icebp, TCG_CALL_NO_WG, noreturn, env)
DEF_HELPER_3(boundw, void, env, tl, int)
DEF_HELPER_3(boundl, void, env, tl, int)

5
target/i386/tcg/emit.c.inc
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@ -1858,7 +1858,10 @@ static void gen_INT(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
static void gen_INT1(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)
{
gen_exception(s, EXCP01_DB);
gen_update_cc_op(s);
gen_update_eip_next(s);
gen_helper_icebp(tcg_env);
s->base.is_jmp = DISAS_NORETURN;
}
static void gen_INT3(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)

20
target/i386/tcg/excp_helper.c
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@ -140,6 +140,26 @@ G_NORETURN void raise_exception_ra(CPUX86State *env, int exception_index,
raise_interrupt2(env, exception_index, 0, 0, 0, retaddr);
}
G_NORETURN void helper_icebp(CPUX86State *env)
{
CPUState *cs = env_cpu(env);
do_end_instruction(env);
/*
* INT1 aka ICEBP generates a trap-like #DB, but it is pretty special.
*
* "Although the ICEBP instruction dispatches through IDT vector 1,
* that event is not interceptable by means of the #DB exception
* intercept". Instead there is a separate fault-like ICEBP intercept.
*/
cs->exception_index = EXCP01_DB;
env->error_code = 0;
env->exception_is_int = 0;
env->exception_next_eip = env->eip;
cpu_loop_exit(cs);
}
G_NORETURN void handle_unaligned_access(CPUX86State *env, vaddr vaddr,
MMUAccessType access_type,
uintptr_t retaddr)

12
target/i386/tcg/helper-tcg.h
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@ -111,7 +111,17 @@ int exception_has_error_code(int intno);
/* smm_helper.c */
void do_smm_enter(X86CPU *cpu);
/* bpt_helper.c */
/* sysemu/bpt_helper.c */
bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update);
/*
* Do the tasks usually performed by gen_eob(). Callers of this function
* should also handle TF as appropriate.
*/
static inline void do_end_instruction(CPUX86State *env)
{
/* needed if sti is just before */
env->hflags &= ~HF_INHIBIT_IRQ_MASK;
env->eflags &= ~HF_RF_MASK;
}
#endif /* I386_HELPER_TCG_H */

13
target/i386/tcg/translate.c
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@ -549,6 +549,19 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d)
}
}
static void gen_update_eip_next(DisasContext *s)
{
assert(s->pc_save != -1);
if (tb_cflags(s->base.tb) & CF_PCREL) {
tcg_gen_addi_tl(cpu_eip, cpu_eip, s->pc - s->pc_save);
} else if (CODE64(s)) {
tcg_gen_movi_tl(cpu_eip, s->pc);
} else {
tcg_gen_movi_tl(cpu_eip, (uint32_t)(s->pc - s->cs_base));
}
s->pc_save = s->pc;
}
static void gen_update_eip_cur(DisasContext *s)
{
assert(s->pc_save != -1);