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target/ppc: add vmulld to INDEX_op_mul_vec case

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Group vmuluwm and vmulld. Make vmulld-specific
changes since it belongs to new ISA 3.1.

Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Message-Id: <20200724045845.89976-3-ljp@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Lijun Pan 2020-07-23 23:58:41 -05:00 committed by David Gibson
parent de55d3b381
commit 73ebe95e8e
2 changed files with 12 additions and 2 deletions
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2
tcg/ppc/tcg-target.h
View File

@ -63,6 +63,7 @@ typedef enum {
tcg_isa_2_06, tcg_isa_2_06,
tcg_isa_2_07, tcg_isa_2_07,
tcg_isa_3_00, tcg_isa_3_00,
tcg_isa_3_10,
} TCGPowerISA; } TCGPowerISA;
extern TCGPowerISA have_isa; extern TCGPowerISA have_isa;
@ -72,6 +73,7 @@ extern bool have_vsx;
#define have_isa_2_06 (have_isa >= tcg_isa_2_06) #define have_isa_2_06 (have_isa >= tcg_isa_2_06)
#define have_isa_2_07 (have_isa >= tcg_isa_2_07) #define have_isa_2_07 (have_isa >= tcg_isa_2_07)
#define have_isa_3_00 (have_isa >= tcg_isa_3_00) #define have_isa_3_00 (have_isa >= tcg_isa_3_00)
#define have_isa_3_10 (have_isa >= tcg_isa_3_10)
/* optional instructions automatically implemented */ /* optional instructions automatically implemented */
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi */ #define TCG_TARGET_HAS_ext8u_i32 0 /* andi */

12
tcg/ppc/tcg-target.inc.c
View File

@ -564,6 +564,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define VMULOUH VX4(72) #define VMULOUH VX4(72)
#define VMULOUW VX4(136) /* v2.07 */ #define VMULOUW VX4(136) /* v2.07 */
#define VMULUWM VX4(137) /* v2.07 */ #define VMULUWM VX4(137) /* v2.07 */
#define VMULLD VX4(457) /* v3.10 */
#define VMSUMUHM VX4(38) #define VMSUMUHM VX4(38)
#define VMRGHB VX4(12) #define VMRGHB VX4(12)
@ -3022,6 +3023,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
return -1; return -1;
case MO_32: case MO_32:
return have_isa_2_07 ? 1 : -1; return have_isa_2_07 ? 1 : -1;
case MO_64:
return have_isa_3_10;
} }
return 0; return 0;
case INDEX_op_bitsel_vec: case INDEX_op_bitsel_vec:
@ -3158,6 +3161,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const uint32_t static const uint32_t
add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
mul_op[4] = { 0, 0, VMULUWM, VMULLD },
neg_op[4] = { 0, 0, VNEGW, VNEGD }, neg_op[4] = { 0, 0, VNEGW, VNEGD },
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
@ -3208,8 +3212,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
a1 = 0; a1 = 0;
break; break;
case INDEX_op_mul_vec: case INDEX_op_mul_vec:
tcg_debug_assert(vece == MO_32 && have_isa_2_07); insn = mul_op[vece];
insn = VMULUWM;
break; break;
case INDEX_op_ssadd_vec: case INDEX_op_ssadd_vec:
insn = ssadd_op[vece]; insn = ssadd_op[vece];
@ -3729,6 +3732,11 @@ static void tcg_target_init(TCGContext *s)
have_isa = tcg_isa_3_00; have_isa = tcg_isa_3_00;
} }
#endif #endif
#ifdef PPC_FEATURE2_ARCH_3_10
if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
have_isa = tcg_isa_3_10;
}
#endif
#ifdef PPC_FEATURE2_HAS_ISEL #ifdef PPC_FEATURE2_HAS_ISEL
/* Prefer explicit instruction from the kernel. */ /* Prefer explicit instruction from the kernel. */