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target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions

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These instructions used to load from memory to GPR via indexed address
divided by base and index parts in GPR registers.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-4-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Siarhei Volkau 2023-06-08 13:41:52 +03:00 committed by Philippe Mathieu-Daudé
parent 1980fa0a58
commit 73c260c1a6
1 changed files with 82 additions and 1 deletions
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83
target/mips/tcg/mxu_translate.c
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@ -304,7 +304,7 @@
* │ ├─ 110 ─ OPC_MXU_S32OR
* │ └─ 111 ─ OPC_MXU_S32XOR
* │
* │ 7..5
* │ 8..6
* ├─ 101000 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_LXB
* │ ├─ 001 ─ OPC_MXU_LXH
* ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_LXW
@ -366,6 +366,7 @@ enum {
OPC_MXU__POOL11 = 0x17,
OPC_MXU_S8LDD = 0x22,
OPC_MXU__POOL16 = 0x27,
OPC_MXU__POOL17 = 0x28,
OPC_MXU_S32M2I = 0x2E,
OPC_MXU_S32I2M = 0x2F,
OPC_MXU__POOL19 = 0x38,
@ -403,6 +404,17 @@ enum {
OPC_MXU_S32XOR = 0x07,
};
/*
* MXU pool 17
*/
enum {
OPC_MXU_LXB = 0x00,
OPC_MXU_LXH = 0x01,
OPC_MXU_LXW = 0x03,
OPC_MXU_LXBU = 0x04,
OPC_MXU_LXHU = 0x05,
};
/*
* MXU pool 19
*/
@ -918,6 +930,38 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,
}
}
/*
* LXW Ra, Rb, Rc, STRD2 - Load a word from memory to GPR
* LXB Ra, Rb, Rc, STRD2 - Load a byte from memory to GPR,
* sign extending to GPR size.
* LXH Ra, Rb, Rc, STRD2 - Load a byte from memory to GPR,
* sign extending to GPR size.
* LXBU Ra, Rb, Rc, STRD2 - Load a halfword from memory to GPR,
* zero extending to GPR size.
* LXHU Ra, Rb, Rc, STRD2 - Load a halfword from memory to GPR,
* zero extending to GPR size.
*/
static void gen_mxu_lxx(DisasContext *ctx, uint32_t strd2, MemOp mop)
{
TCGv t0, t1;
uint32_t Ra, Rb, Rc;
t0 = tcg_temp_new();
t1 = tcg_temp_new();
Ra = extract32(ctx->opcode, 11, 5);
Rc = extract32(ctx->opcode, 16, 5);
Rb = extract32(ctx->opcode, 21, 5);
gen_load_gpr(t0, Rb);
gen_load_gpr(t1, Rc);
tcg_gen_shli_tl(t1, t1, strd2);
tcg_gen_add_tl(t0, t0, t1);
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mop | ctx->default_tcg_memop_mask);
gen_store_gpr(t1, Ra);
}
/*
* S32STDV XRa, Rb, Rc, STRD2 - Load a word from memory to XRF
* S32STDVR XRa, Rb, Rc, STRD2 - Load a word from memory to XRF
@ -1716,6 +1760,40 @@ static void decode_opc_mxu__pool16(DisasContext *ctx)
}
}
static void decode_opc_mxu__pool17(DisasContext *ctx)
{
uint32_t opcode = extract32(ctx->opcode, 6, 3);
uint32_t strd2 = extract32(ctx->opcode, 9, 2);
if (strd2 > 2) {
MIPS_INVAL("decode_opc_mxu");
gen_reserved_instruction(ctx);
return;
}
switch (opcode) {
case OPC_MXU_LXW:
gen_mxu_lxx(ctx, strd2, MO_TE | MO_UL);
break;
case OPC_MXU_LXB:
gen_mxu_lxx(ctx, strd2, MO_TE | MO_SB);
break;
case OPC_MXU_LXH:
gen_mxu_lxx(ctx, strd2, MO_TE | MO_SW);
break;
case OPC_MXU_LXBU:
gen_mxu_lxx(ctx, strd2, MO_TE | MO_UB);
break;
case OPC_MXU_LXHU:
gen_mxu_lxx(ctx, strd2, MO_TE | MO_UW);
break;
default:
MIPS_INVAL("decode_opc_mxu");
gen_reserved_instruction(ctx);
break;
}
}
static void decode_opc_mxu__pool19(DisasContext *ctx)
{
uint32_t opcode = extract32(ctx->opcode, 22, 2);
@ -1794,6 +1872,9 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
case OPC_MXU__POOL16:
decode_opc_mxu__pool16(ctx);
break;
case OPC_MXU__POOL17:
decode_opc_mxu__pool17(ctx);
break;
case OPC_MXU__POOL19:
decode_opc_mxu__pool19(ctx);
break;