mirror of https://gitlab.com/qemu-project/qemu
softfloat: Don't execute divdeu without power7
The divdeu instruction was added to ISA 2.06 (Power7).
Exclude this block from older cpus.
Fixes: 27ae5109a2
(softfloat: Specialize udiv_qrnnd for ppc64)
Reported-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -647,8 +647,8 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
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asm("dlgr %0, %1" : "+r"(n) : "r"(d));
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asm("dlgr %0, %1" : "+r"(n) : "r"(d));
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*r = n >> 64;
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*r = n >> 64;
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return n;
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return n;
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#elif defined(_ARCH_PPC64)
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#elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7)
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/* From Power ISA 3.0B, programming note for divdeu. */
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/* From Power ISA 2.06, programming note for divdeu. */
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uint64_t q1, q2, Q, r1, r2, R;
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uint64_t q1, q2, Q, r1, r2, R;
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asm("divdeu %0,%2,%4; divdu %1,%3,%4"
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asm("divdeu %0,%2,%4; divdu %1,%3,%4"
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: "=&r"(q1), "=r"(q2)
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: "=&r"(q1), "=r"(q2)
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