mips: Decide to map PAGE_EXEC in map_address
This commit addresses QEMU Bug #1825311: mips_cpu_handle_mmu_fault renders all accessed pages executable It allows finer-grained control over whether the accessed page should be executable by moving the decision to the underlying map_address function, which has more information for this. As a result, pages that have the XI bit set in the TLB and are accessed for read/write, don't suddenly end up being executable. Fixes: https://bugs.launchpad.net/qemu/+bug/1825311 Fixes: 2fb58b73746e ('target-mips: add RI and XI fields to TLB entry') Signed-off-by: Jakub Jermář <jakub.jermar@kernkonzept.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190517123533.868479-1-jakub.jermar@kernkonzept.com>
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@ -43,7 +43,7 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
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target_ulong address, int rw, int access_type)
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{
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TLBRET_MATCH;
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}
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@ -61,7 +61,7 @@ int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
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else
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TLBRET_MATCH;
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}
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@ -101,6 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
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*prot = PAGE_READ;
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if (n ? tlb->D1 : tlb->D0)
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*prot |= PAGE_WRITE;
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if (!(n ? tlb->XI1 : tlb->XI0)) {
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*prot |= PAGE_EXEC;
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}
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return TLBRET_MATCH;
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}
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return TLBRET_DIRTY;
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@ -182,7 +185,7 @@ static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical,
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} else {
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/* The segment is unmapped */
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*physical = physical_base | (real_address & segmask);
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*prot = PAGE_READ | PAGE_WRITE;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return TLBRET_MATCH;
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}
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}
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@ -907,7 +910,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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}
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if (ret == TLBRET_MATCH) {
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
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physical & TARGET_PAGE_MASK, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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@ -927,7 +930,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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access_type, mips_access_type, mmu_idx);
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if (ret == TLBRET_MATCH) {
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
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physical & TARGET_PAGE_MASK, prot,
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mmu_idx, TARGET_PAGE_SIZE);
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return true;
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}
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