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target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc

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Check for Zve32f/Zve64d can overlap check for F/D.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-10-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Weiwei Li 2023-02-15 10:05:34 +08:00 committed by Palmer Dabbelt
parent 3f4a5a5314
commit 732b902dd5
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GPG Key ID: 2E1319F35FBB1889
1 changed files with 4 additions and 4 deletions
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8
target/riscv/insn_trans/trans_rvv.c.inc
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@ -41,9 +41,9 @@ static bool require_rvf(DisasContext *s)
switch (s->sew) {
case MO_16:
case MO_32:
return has_ext(s, RVF);
return s->cfg_ptr->ext_zve32f;
case MO_64:
return has_ext(s, RVD);
return s->cfg_ptr->ext_zve64d;
default:
return false;
}
@ -58,9 +58,9 @@ static bool require_scale_rvf(DisasContext *s)
switch (s->sew) {
case MO_8:
case MO_16:
return has_ext(s, RVF);
return s->cfg_ptr->ext_zve32f;
case MO_32:
return has_ext(s, RVD);
return s->cfg_ptr->ext_zve64d;
default:
return false;
}