openpic: add Shared MSI support
The OpenPIC allows MSI access through shared MSI registers. Implement them for the MPC8544 MPIC, so we can support MSIs. Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf
parent
dbbbfd6058
commit
732aa6ec26
150
hw/openpic.c
150
hw/openpic.c
@ -38,6 +38,7 @@
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#include "pci.h"
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#include "openpic.h"
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#include "sysbus.h"
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#include "msi.h"
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//#define DEBUG_OPENPIC
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@ -52,6 +53,7 @@
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#define MAX_TMR 4
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#define VECTOR_BITS 8
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#define MAX_IPI 4
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#define MAX_MSI 8
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#define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR)
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#define VID 0x03 /* MPIC version ID */
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@ -63,6 +65,8 @@
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#define OPENPIC_GLB_REG_SIZE 0x10F0
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#define OPENPIC_TMR_REG_START 0x10F0
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#define OPENPIC_TMR_REG_SIZE 0x220
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#define OPENPIC_MSI_REG_START 0x1600
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#define OPENPIC_MSI_REG_SIZE 0x200
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#define OPENPIC_SRC_REG_START 0x10000
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#define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
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#define OPENPIC_CPU_REG_START 0x20000
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@ -127,6 +131,12 @@
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#define IDR_P1_SHIFT 1
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#define IDR_P0_SHIFT 0
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#define MSIIR_OFFSET 0x140
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#define MSIIR_SRS_SHIFT 29
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#define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
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#define MSIIR_IBS_SHIFT 24
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#define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT)
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#define BF_WIDTH(_bits_) \
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(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
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@ -209,7 +219,7 @@ typedef struct OpenPICState {
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uint32_t brr1;
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/* Sub-regions */
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MemoryRegion sub_io_mem[7];
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MemoryRegion sub_io_mem[5];
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/* Global registers */
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uint32_t frep; /* Feature reporting register */
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@ -227,9 +237,14 @@ typedef struct OpenPICState {
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uint32_t ticc; /* Global timer current count register */
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uint32_t tibc; /* Global timer base count register */
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} timers[MAX_TMR];
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/* Shared MSI registers */
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struct {
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uint32_t msir; /* Shared Message Signaled Interrupt Register */
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} msi[MAX_MSI];
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uint32_t max_irq;
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uint32_t irq_ipi0;
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uint32_t irq_tim0;
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uint32_t irq_msi;
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} OpenPICState;
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static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src);
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@ -704,6 +719,68 @@ static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len)
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return retval;
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}
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static void openpic_msi_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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OpenPICState *opp = opaque;
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int idx = opp->irq_msi;
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int srs, ibs;
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DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
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if (addr & 0xF) {
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return;
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}
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switch (addr) {
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case MSIIR_OFFSET:
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srs = val >> MSIIR_SRS_SHIFT;
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idx += srs;
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ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT;
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opp->msi[srs].msir |= 1 << ibs;
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openpic_set_irq(opp, idx, 1);
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break;
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default:
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/* most registers are read-only, thus ignored */
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break;
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}
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}
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static uint64_t openpic_msi_read(void *opaque, hwaddr addr, unsigned size)
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{
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OpenPICState *opp = opaque;
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uint64_t r = 0;
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int i, srs;
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DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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if (addr & 0xF) {
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return -1;
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}
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srs = addr >> 4;
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switch (addr) {
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case 0x00:
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case 0x10:
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case 0x20:
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case 0x30:
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case 0x40:
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case 0x50:
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case 0x60:
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case 0x70: /* MSIRs */
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r = opp->msi[srs].msir;
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/* Clear on read */
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opp->msi[srs].msir = 0;
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break;
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case 0x120: /* MSISR */
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for (i = 0; i < MAX_MSI; i++) {
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r |= (opp->msi[i].msir ? 1 : 0) << i;
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}
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break;
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}
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return r;
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}
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static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
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uint32_t val, int idx)
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{
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@ -932,6 +1009,26 @@ static const MemoryRegionOps openpic_src_ops_be = {
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},
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};
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static const MemoryRegionOps openpic_msi_ops_le = {
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.read = openpic_msi_read,
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.write = openpic_msi_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static const MemoryRegionOps openpic_msi_ops_be = {
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.read = openpic_msi_read,
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.write = openpic_msi_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void openpic_save_IRQ_queue(QEMUFile* f, IRQ_queue_t *q)
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{
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unsigned int i;
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@ -1039,6 +1136,7 @@ static void openpic_irq_raise(OpenPICState *opp, int n_CPU, IRQ_src_t *src)
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struct memreg {
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const char *name;
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MemoryRegionOps const *ops;
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bool map;
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hwaddr start_addr;
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ram_addr_t size;
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};
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@ -1047,27 +1145,31 @@ static int openpic_init(SysBusDevice *dev)
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{
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OpenPICState *opp = FROM_SYSBUS(typeof (*opp), dev);
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int i, j;
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const struct memreg list_le[] = {
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{"glb", &openpic_glb_ops_le, OPENPIC_GLB_REG_START,
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OPENPIC_GLB_REG_SIZE},
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{"tmr", &openpic_tmr_ops_le, OPENPIC_TMR_REG_START,
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OPENPIC_TMR_REG_SIZE},
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{"src", &openpic_src_ops_le, OPENPIC_SRC_REG_START,
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OPENPIC_SRC_REG_SIZE},
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{"cpu", &openpic_cpu_ops_le, OPENPIC_CPU_REG_START,
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OPENPIC_CPU_REG_SIZE},
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struct memreg list_le[] = {
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{"glb", &openpic_glb_ops_le, true,
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OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
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{"tmr", &openpic_tmr_ops_le, true,
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OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
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{"msi", &openpic_msi_ops_le, true,
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OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE},
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{"src", &openpic_src_ops_le, true,
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OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
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{"cpu", &openpic_cpu_ops_le, true,
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OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
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};
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const struct memreg list_be[] = {
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{"glb", &openpic_glb_ops_be, OPENPIC_GLB_REG_START,
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OPENPIC_GLB_REG_SIZE},
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{"tmr", &openpic_tmr_ops_be, OPENPIC_TMR_REG_START,
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OPENPIC_TMR_REG_SIZE},
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{"src", &openpic_src_ops_be, OPENPIC_SRC_REG_START,
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OPENPIC_SRC_REG_SIZE},
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{"cpu", &openpic_cpu_ops_be, OPENPIC_CPU_REG_START,
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OPENPIC_CPU_REG_SIZE},
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struct memreg list_be[] = {
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{"glb", &openpic_glb_ops_be, true,
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OPENPIC_GLB_REG_START, OPENPIC_GLB_REG_SIZE},
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{"tmr", &openpic_tmr_ops_be, true,
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OPENPIC_TMR_REG_START, OPENPIC_TMR_REG_SIZE},
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{"msi", &openpic_msi_ops_be, true,
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OPENPIC_MSI_REG_START, OPENPIC_MSI_REG_SIZE},
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{"src", &openpic_src_ops_be, true,
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OPENPIC_SRC_REG_START, OPENPIC_SRC_REG_SIZE},
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{"cpu", &openpic_cpu_ops_be, true,
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OPENPIC_CPU_REG_START, OPENPIC_CPU_REG_SIZE},
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};
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struct memreg const *list;
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struct memreg *list;
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switch (opp->model) {
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case OPENPIC_MODEL_FSL_MPIC_20:
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@ -1083,7 +1185,9 @@ static int openpic_init(SysBusDevice *dev)
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opp->max_irq = FSL_MPIC_20_MAX_IRQ;
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opp->irq_ipi0 = FSL_MPIC_20_IPI_IRQ;
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opp->irq_tim0 = FSL_MPIC_20_TMR_IRQ;
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opp->irq_msi = FSL_MPIC_20_MSI_IRQ;
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opp->brr1 = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
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msi_supported = true;
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list = list_be;
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break;
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case OPENPIC_MODEL_RAVEN:
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@ -1099,6 +1203,8 @@ static int openpic_init(SysBusDevice *dev)
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opp->irq_tim0 = RAVEN_TMR_IRQ;
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opp->brr1 = -1;
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list = list_le;
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/* Don't map MSI region */
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list[2].map = false;
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/* Only UP supported today */
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if (opp->nb_cpus != 1) {
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@ -1110,6 +1216,10 @@ static int openpic_init(SysBusDevice *dev)
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memory_region_init(&opp->mem, "openpic", 0x40000);
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for (i = 0; i < ARRAY_SIZE(list_le); i++) {
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if (!list[i].map) {
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continue;
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}
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memory_region_init_io(&opp->sub_io_mem[i], list[i].ops, opp,
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list[i].name, list[i].size);
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