tcg-arm: Make use of conditional availability of opcodes for divide
We can now detect and use divide instructions at runtime, rather than having to restrict their availability to compile-time. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0;
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#endif
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#undef USE_ARMV7_INSTRUCTIONS
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#ifndef use_idiv_instructions
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bool use_idiv_instructions;
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#endif
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#ifdef CONFIG_GETAUXVAL
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# include <sys/auxv.h>
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#endif
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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"%r0",
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@ -2029,16 +2036,21 @@ static const TCGTargetOpDef arm_op_defs[] = {
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{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
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#if TCG_TARGET_HAS_div_i32
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{ INDEX_op_div_i32, { "r", "r", "r" } },
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{ INDEX_op_divu_i32, { "r", "r", "r" } },
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#endif
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{ -1 },
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};
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static void tcg_target_init(TCGContext *s)
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{
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#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
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{
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unsigned long hwcap = getauxval(AT_HWCAP);
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use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
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}
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#endif
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tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
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tcg_regset_set32(tcg_target_call_clobber_regs, 0,
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(1 << TCG_REG_R0) |
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@ -49,6 +49,13 @@ typedef enum {
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#define TCG_TARGET_NB_REGS 16
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#ifdef __ARM_ARCH_EXT_IDIV__
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#define use_idiv_instructions 1
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#else
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extern bool use_idiv_instructions;
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#endif
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_R13
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#define TCG_TARGET_STACK_ALIGN 8
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@ -73,12 +80,7 @@ typedef enum {
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_muls2_i32 1
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#ifdef __ARM_ARCH_EXT_IDIV__
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#define TCG_TARGET_HAS_div_i32 1
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#else
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#define TCG_TARGET_HAS_div_i32 0
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#endif
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#define TCG_TARGET_HAS_div_i32 use_idiv_instructions
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#define TCG_TARGET_HAS_rem_i32 0
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extern bool tcg_target_deposit_valid(int ofs, int len);
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