hw/misc/bcm2835_cprman: add a clock mux skeleton implementation
The clock multiplexers are the last clock stage in the CPRMAN. Each mux outputs one clock signal that goes out of the CPRMAN to the SoC peripherals. Each mux has at most 10 sources. The sources 0 to 3 are common to all muxes. They are: 0. ground (no clock signal) 1. the main oscillator (xosc) 2. "test debug 0" clock 3. "test debug 1" clock Test debug 0 and 1 are actual clock muxes that can be used as sources to other muxes (for debug purpose). Sources 4 to 9 are mux specific and can be unpopulated (grounded). Those sources are fed by the PLL channels outputs. One corner case exists for DSI0E and DSI0P muxes. They have their source number 4 connected to an intermediate multiplexer that can select between PLLA-DSI0 and PLLD-DSI0 channel. This multiplexer is called DSI0HSCK and is not a clock mux as such. It is really a simple mux from the hardware point of view (see https://elinux.org/The_Undocumented_Pi). This mux is not implemented in this commit. Note that there is some muxes for which sources are unknown (because of a lack of documentation). For those cases all the sources are connected to ground in this implementation. Each clock mux output is exported by the CPRMAN at the qdev level, adding the suffix '-out' to the mux name to form the output clock name. (E.g. the 'uart' mux sees its output exported as 'uart-out' at the CPRMAN level.) Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luc Michel <luc@lmichel.fr> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Luc Michel
Peter Maydell
parent
9574581112
commit
7281362484
@ -38,6 +38,9 @@
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*
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* The page at https://elinux.org/The_Undocumented_Pi gives the actual clock
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* tree configuration.
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*
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* The CPRMAN exposes clock outputs with the name of the clock mux suffixed
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* with "-out" (e.g. "uart-out", "h264-out", ...).
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*/
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#include "qemu/osdep.h"
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@ -226,6 +229,65 @@ static const TypeInfo cprman_pll_channel_info = {
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};
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/* clock mux */
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static void clock_mux_update(CprmanClockMuxState *mux)
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{
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clock_update(mux->out, 0);
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}
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static void clock_mux_src_update(void *opaque)
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{
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CprmanClockMuxState **backref = opaque;
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CprmanClockMuxState *s = *backref;
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clock_mux_update(s);
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}
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static void clock_mux_init(Object *obj)
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{
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CprmanClockMuxState *s = CPRMAN_CLOCK_MUX(obj);
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size_t i;
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for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) {
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char *name = g_strdup_printf("srcs[%zu]", i);
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s->backref[i] = s;
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s->srcs[i] = qdev_init_clock_in(DEVICE(s), name,
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clock_mux_src_update,
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&s->backref[i]);
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g_free(name);
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}
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s->out = qdev_init_clock_out(DEVICE(s), "out");
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}
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static const VMStateDescription clock_mux_vmstate = {
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.name = TYPE_CPRMAN_CLOCK_MUX,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_ARRAY_CLOCK(srcs, CprmanClockMuxState,
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CPRMAN_NUM_CLOCK_MUX_SRC),
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VMSTATE_END_OF_LIST()
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}
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};
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static void clock_mux_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &clock_mux_vmstate;
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}
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static const TypeInfo cprman_clock_mux_info = {
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.name = TYPE_CPRMAN_CLOCK_MUX,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(CprmanClockMuxState),
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.class_init = clock_mux_class_init,
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.instance_init = clock_mux_init,
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};
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/* CPRMAN "top level" model */
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static uint32_t get_cm_lock(const BCM2835CprmanState *s)
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@ -293,6 +355,20 @@ static inline void update_channel_from_a2w(BCM2835CprmanState *s, size_t idx)
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}
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}
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static inline void update_mux_from_cm(BCM2835CprmanState *s, size_t idx)
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{
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size_t i;
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for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
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if ((CLOCK_MUX_INIT_INFO[i].cm_offset == idx) ||
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(CLOCK_MUX_INIT_INFO[i].cm_offset + 4 == idx)) {
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/* matches CM_CTL or CM_DIV mux register */
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clock_mux_update(&s->clock_muxes[i]);
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return;
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}
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}
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}
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#define CASE_PLL_A2W_REGS(pll_) \
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case R_A2W_ ## pll_ ## _CTRL: \
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case R_A2W_ ## pll_ ## _ANA0: \
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@ -365,6 +441,15 @@ static void cprman_write(void *opaque, hwaddr offset,
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case R_A2W_PLLB_ARM:
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update_channel_from_a2w(s, idx);
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break;
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case R_CM_GNRICCTL ... R_CM_SMIDIV:
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case R_CM_TCNTCNT ... R_CM_VECDIV:
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case R_CM_PULSECTL ... R_CM_PULSEDIV:
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case R_CM_SDCCTL ... R_CM_ARMCTL:
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case R_CM_AVEOCTL ... R_CM_EMMCDIV:
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case R_CM_EMMC2CTL ... R_CM_EMMC2DIV:
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update_mux_from_cm(s, idx);
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break;
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}
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}
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@ -404,6 +489,10 @@ static void cprman_reset(DeviceState *dev)
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device_cold_reset(DEVICE(&s->channels[i]));
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}
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for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
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device_cold_reset(DEVICE(&s->clock_muxes[i]));
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}
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clock_update_hz(s->xosc, s->xosc_freq);
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}
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@ -425,13 +514,64 @@ static void cprman_init(Object *obj)
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set_pll_channel_init_info(s, &s->channels[i], i);
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}
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for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
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char *alias;
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object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name,
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&s->clock_muxes[i],
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TYPE_CPRMAN_CLOCK_MUX);
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set_clock_mux_init_info(s, &s->clock_muxes[i], i);
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/* Expose muxes output as CPRMAN outputs */
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alias = g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name);
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qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), alias);
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g_free(alias);
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}
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s->xosc = clock_new(obj, "xosc");
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s->gnd = clock_new(obj, "gnd");
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clock_set(s->gnd, 0);
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memory_region_init_io(&s->iomem, obj, &cprman_ops,
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s, "bcm2835-cprman", 0x2000);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
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}
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static void connect_mux_sources(BCM2835CprmanState *s,
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CprmanClockMuxState *mux,
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const CprmanPllChannel *clk_mapping)
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{
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size_t i;
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Clock *td0 = s->clock_muxes[CPRMAN_CLOCK_TD0].out;
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Clock *td1 = s->clock_muxes[CPRMAN_CLOCK_TD1].out;
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/* For sources from 0 to 3. Source 4 to 9 are mux specific */
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Clock * const CLK_SRC_MAPPING[] = {
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[CPRMAN_CLOCK_SRC_GND] = s->gnd,
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[CPRMAN_CLOCK_SRC_XOSC] = s->xosc,
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[CPRMAN_CLOCK_SRC_TD0] = td0,
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[CPRMAN_CLOCK_SRC_TD1] = td1,
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};
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for (i = 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) {
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CprmanPllChannel mapping = clk_mapping[i];
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Clock *src;
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if (mapping == CPRMAN_CLOCK_SRC_FORCE_GROUND) {
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src = s->gnd;
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} else if (mapping == CPRMAN_CLOCK_SRC_DSI0HSCK) {
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src = s->gnd; /* TODO */
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} else if (i < CPRMAN_CLOCK_SRC_PLLA) {
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src = CLK_SRC_MAPPING[i];
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} else {
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src = s->channels[mapping].out;
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}
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clock_set_source(mux->srcs[i], src);
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}
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}
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static void cprman_realize(DeviceState *dev, Error **errp)
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{
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BCM2835CprmanState *s = CPRMAN(dev);
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@ -458,6 +598,16 @@ static void cprman_realize(DeviceState *dev, Error **errp)
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return;
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}
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}
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for (i = 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
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CprmanClockMuxState *clock_mux = &s->clock_muxes[i];
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connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mapping);
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if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) {
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return;
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}
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}
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}
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static const VMStateDescription cprman_vmstate = {
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@ -498,6 +648,7 @@ static void cprman_register_types(void)
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type_register_static(&cprman_info);
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type_register_static(&cprman_pll_info);
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type_register_static(&cprman_pll_channel_info);
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type_register_static(&cprman_clock_mux_info);
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}
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type_init(cprman_register_types);
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@ -54,8 +54,69 @@ typedef enum CprmanPllChannel {
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CPRMAN_PLLB_CHANNEL_ARM,
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CPRMAN_NUM_PLL_CHANNEL,
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/* Special values used when connecting clock sources to clocks */
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CPRMAN_CLOCK_SRC_NORMAL = -1,
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CPRMAN_CLOCK_SRC_FORCE_GROUND = -2,
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CPRMAN_CLOCK_SRC_DSI0HSCK = -3,
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} CprmanPllChannel;
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typedef enum CprmanClockMux {
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CPRMAN_CLOCK_GNRIC,
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CPRMAN_CLOCK_VPU,
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CPRMAN_CLOCK_SYS,
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CPRMAN_CLOCK_PERIA,
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CPRMAN_CLOCK_PERII,
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CPRMAN_CLOCK_H264,
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CPRMAN_CLOCK_ISP,
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CPRMAN_CLOCK_V3D,
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CPRMAN_CLOCK_CAM0,
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CPRMAN_CLOCK_CAM1,
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CPRMAN_CLOCK_CCP2,
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CPRMAN_CLOCK_DSI0E,
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CPRMAN_CLOCK_DSI0P,
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CPRMAN_CLOCK_DPI,
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CPRMAN_CLOCK_GP0,
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CPRMAN_CLOCK_GP1,
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CPRMAN_CLOCK_GP2,
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CPRMAN_CLOCK_HSM,
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CPRMAN_CLOCK_OTP,
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CPRMAN_CLOCK_PCM,
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CPRMAN_CLOCK_PWM,
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CPRMAN_CLOCK_SLIM,
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CPRMAN_CLOCK_SMI,
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CPRMAN_CLOCK_TEC,
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CPRMAN_CLOCK_TD0,
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CPRMAN_CLOCK_TD1,
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CPRMAN_CLOCK_TSENS,
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CPRMAN_CLOCK_TIMER,
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CPRMAN_CLOCK_UART,
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CPRMAN_CLOCK_VEC,
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CPRMAN_CLOCK_PULSE,
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CPRMAN_CLOCK_SDC,
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CPRMAN_CLOCK_ARM,
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CPRMAN_CLOCK_AVEO,
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CPRMAN_CLOCK_EMMC,
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CPRMAN_CLOCK_EMMC2,
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CPRMAN_NUM_CLOCK_MUX
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} CprmanClockMux;
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typedef enum CprmanClockMuxSource {
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CPRMAN_CLOCK_SRC_GND = 0,
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CPRMAN_CLOCK_SRC_XOSC,
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CPRMAN_CLOCK_SRC_TD0,
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CPRMAN_CLOCK_SRC_TD1,
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CPRMAN_CLOCK_SRC_PLLA,
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CPRMAN_CLOCK_SRC_PLLC,
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CPRMAN_CLOCK_SRC_PLLD,
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CPRMAN_CLOCK_SRC_PLLH,
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CPRMAN_CLOCK_SRC_PLLC_CORE1,
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CPRMAN_CLOCK_SRC_PLLC_CORE2,
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CPRMAN_NUM_CLOCK_MUX_SRC
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} CprmanClockMuxSource;
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typedef struct CprmanPllState {
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/*< private >*/
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DeviceState parent_obj;
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@ -91,6 +152,28 @@ typedef struct CprmanPllChannelState {
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Clock *out;
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} CprmanPllChannelState;
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typedef struct CprmanClockMuxState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CprmanClockMux id;
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uint32_t *reg_ctl;
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uint32_t *reg_div;
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int int_bits;
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int frac_bits;
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Clock *srcs[CPRMAN_NUM_CLOCK_MUX_SRC];
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Clock *out;
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/*
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* Used by clock srcs update callback to retrieve both the clock and the
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* source number.
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*/
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struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC];
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} CprmanClockMuxState;
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struct BCM2835CprmanState {
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/*< private >*/
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SysBusDevice parent_obj;
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@ -100,11 +183,13 @@ struct BCM2835CprmanState {
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CprmanPllState plls[CPRMAN_NUM_PLL];
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CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
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CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX];
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uint32_t regs[CPRMAN_NUM_REGS];
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uint32_t xosc_freq;
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Clock *xosc;
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Clock *gnd;
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};
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#endif
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@ -14,11 +14,14 @@
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#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
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#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
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#define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
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DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
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TYPE_CPRMAN_PLL)
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DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PLL_CHANNEL,
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TYPE_CPRMAN_PLL_CHANNEL)
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DECLARE_INSTANCE_CHECKER(CprmanClockMuxState, CPRMAN_CLOCK_MUX,
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TYPE_CPRMAN_CLOCK_MUX)
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/* Register map */
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@ -128,6 +131,90 @@ REG32(A2W_PLLH_STS, 0x1660)
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REG32(A2W_PLLB_ARM, 0x13e0)
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/* Clock muxes */
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REG32(CM_GNRICCTL, 0x000)
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FIELD(CM_CLOCKx_CTL, SRC, 0, 4)
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FIELD(CM_CLOCKx_CTL, ENABLE, 4, 1)
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FIELD(CM_CLOCKx_CTL, KILL, 5, 1)
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FIELD(CM_CLOCKx_CTL, GATE, 6, 1)
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FIELD(CM_CLOCKx_CTL, BUSY, 7, 1)
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FIELD(CM_CLOCKx_CTL, BUSYD, 8, 1)
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FIELD(CM_CLOCKx_CTL, MASH, 9, 2)
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FIELD(CM_CLOCKx_CTL, FLIP, 11, 1)
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REG32(CM_GNRICDIV, 0x004)
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FIELD(CM_CLOCKx_DIV, FRAC, 0, 12)
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REG32(CM_VPUCTL, 0x008)
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REG32(CM_VPUDIV, 0x00c)
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REG32(CM_SYSCTL, 0x010)
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REG32(CM_SYSDIV, 0x014)
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REG32(CM_PERIACTL, 0x018)
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REG32(CM_PERIADIV, 0x01c)
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REG32(CM_PERIICTL, 0x020)
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REG32(CM_PERIIDIV, 0x024)
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REG32(CM_H264CTL, 0x028)
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REG32(CM_H264DIV, 0x02c)
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REG32(CM_ISPCTL, 0x030)
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REG32(CM_ISPDIV, 0x034)
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REG32(CM_V3DCTL, 0x038)
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REG32(CM_V3DDIV, 0x03c)
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REG32(CM_CAM0CTL, 0x040)
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REG32(CM_CAM0DIV, 0x044)
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REG32(CM_CAM1CTL, 0x048)
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REG32(CM_CAM1DIV, 0x04c)
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REG32(CM_CCP2CTL, 0x050)
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REG32(CM_CCP2DIV, 0x054)
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REG32(CM_DSI0ECTL, 0x058)
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REG32(CM_DSI0EDIV, 0x05c)
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REG32(CM_DSI0PCTL, 0x060)
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REG32(CM_DSI0PDIV, 0x064)
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REG32(CM_DPICTL, 0x068)
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REG32(CM_DPIDIV, 0x06c)
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REG32(CM_GP0CTL, 0x070)
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REG32(CM_GP0DIV, 0x074)
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REG32(CM_GP1CTL, 0x078)
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REG32(CM_GP1DIV, 0x07c)
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REG32(CM_GP2CTL, 0x080)
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REG32(CM_GP2DIV, 0x084)
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REG32(CM_HSMCTL, 0x088)
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REG32(CM_HSMDIV, 0x08c)
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REG32(CM_OTPCTL, 0x090)
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REG32(CM_OTPDIV, 0x094)
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REG32(CM_PCMCTL, 0x098)
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REG32(CM_PCMDIV, 0x09c)
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REG32(CM_PWMCTL, 0x0a0)
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REG32(CM_PWMDIV, 0x0a4)
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REG32(CM_SLIMCTL, 0x0a8)
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REG32(CM_SLIMDIV, 0x0ac)
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REG32(CM_SMICTL, 0x0b0)
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REG32(CM_SMIDIV, 0x0b4)
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REG32(CM_TCNTCTL, 0x0c0)
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REG32(CM_TCNTCNT, 0x0c4)
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REG32(CM_TECCTL, 0x0c8)
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REG32(CM_TECDIV, 0x0cc)
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REG32(CM_TD0CTL, 0x0d0)
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REG32(CM_TD0DIV, 0x0d4)
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REG32(CM_TD1CTL, 0x0d8)
|
||||
REG32(CM_TD1DIV, 0x0dc)
|
||||
REG32(CM_TSENSCTL, 0x0e0)
|
||||
REG32(CM_TSENSDIV, 0x0e4)
|
||||
REG32(CM_TIMERCTL, 0x0e8)
|
||||
REG32(CM_TIMERDIV, 0x0ec)
|
||||
REG32(CM_UARTCTL, 0x0f0)
|
||||
REG32(CM_UARTDIV, 0x0f4)
|
||||
REG32(CM_VECCTL, 0x0f8)
|
||||
REG32(CM_VECDIV, 0x0fc)
|
||||
REG32(CM_PULSECTL, 0x190)
|
||||
REG32(CM_PULSEDIV, 0x194)
|
||||
REG32(CM_SDCCTL, 0x1a8)
|
||||
REG32(CM_SDCDIV, 0x1ac)
|
||||
REG32(CM_ARMCTL, 0x1b0)
|
||||
REG32(CM_AVEOCTL, 0x1b8)
|
||||
REG32(CM_AVEODIV, 0x1bc)
|
||||
REG32(CM_EMMCCTL, 0x1c0)
|
||||
REG32(CM_EMMCDIV, 0x1c4)
|
||||
REG32(CM_EMMC2CTL, 0x1d0)
|
||||
REG32(CM_EMMC2DIV, 0x1d4)
|
||||
|
||||
/* misc registers */
|
||||
REG32(CM_LOCK, 0x114)
|
||||
FIELD(CM_LOCK, FLOCKH, 12, 1)
|
||||
@ -319,4 +406,339 @@ static inline void set_pll_channel_init_info(BCM2835CprmanState *s,
|
||||
channel->fixed_divider = PLL_CHANNEL_INIT_INFO[id].fixed_divider;
|
||||
}
|
||||
|
||||
/* Clock mux init info */
|
||||
typedef struct ClockMuxInitInfo {
|
||||
const char *name;
|
||||
size_t cm_offset; /* cm_offset[0]->CM_CTL, cm_offset[1]->CM_DIV */
|
||||
int int_bits;
|
||||
int frac_bits;
|
||||
|
||||
CprmanPllChannel src_mapping[CPRMAN_NUM_CLOCK_MUX_SRC];
|
||||
} ClockMuxInitInfo;
|
||||
|
||||
/*
|
||||
* Each clock mux can have up to 10 sources. Sources 0 to 3 are always the
|
||||
* same (ground, xosc, td0, td1). Sources 4 to 9 are mux specific, and are not
|
||||
* always populated. The following macros catch all those cases.
|
||||
*/
|
||||
|
||||
/* Unknown mapping. Connect everything to ground */
|
||||
#define SRC_MAPPING_INFO_unknown \
|
||||
.src_mapping = { \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, /* gnd */ \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, /* xosc */ \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, /* test debug 0 */ \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, /* test debug 1 */ \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll a */ \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c */ \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll d */ \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll h */ \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core1 */ \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core2 */ \
|
||||
}
|
||||
|
||||
/* Only the oscillator and the two test debug clocks */
|
||||
#define SRC_MAPPING_INFO_xosc \
|
||||
.src_mapping = { \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
}
|
||||
|
||||
/* All the PLL "core" channels */
|
||||
#define SRC_MAPPING_INFO_core \
|
||||
.src_mapping = { \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_PLLA_CHANNEL_CORE, \
|
||||
CPRMAN_PLLC_CHANNEL_CORE0, \
|
||||
CPRMAN_PLLD_CHANNEL_CORE, \
|
||||
CPRMAN_PLLH_CHANNEL_AUX, \
|
||||
CPRMAN_PLLC_CHANNEL_CORE1, \
|
||||
CPRMAN_PLLC_CHANNEL_CORE2, \
|
||||
}
|
||||
|
||||
/* All the PLL "per" channels */
|
||||
#define SRC_MAPPING_INFO_periph \
|
||||
.src_mapping = { \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_PLLA_CHANNEL_PER, \
|
||||
CPRMAN_PLLC_CHANNEL_PER, \
|
||||
CPRMAN_PLLD_CHANNEL_PER, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
}
|
||||
|
||||
/*
|
||||
* The DSI0 channels. This one got an intermediate mux between the PLL channels
|
||||
* and the clock input.
|
||||
*/
|
||||
#define SRC_MAPPING_INFO_dsi0 \
|
||||
.src_mapping = { \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_DSI0HSCK, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
}
|
||||
|
||||
/* The DSI1 channel */
|
||||
#define SRC_MAPPING_INFO_dsi1 \
|
||||
.src_mapping = { \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_CLOCK_SRC_NORMAL, \
|
||||
CPRMAN_PLLD_CHANNEL_DSI1, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
CPRMAN_CLOCK_SRC_FORCE_GROUND, \
|
||||
}
|
||||
|
||||
#define FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO(kind_) \
|
||||
SRC_MAPPING_INFO_ ## kind_
|
||||
|
||||
#define FILL_CLOCK_MUX_INIT_INFO(clock_, kind_) \
|
||||
.cm_offset = R_CM_ ## clock_ ## CTL, \
|
||||
FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO(kind_)
|
||||
|
||||
static ClockMuxInitInfo CLOCK_MUX_INIT_INFO[] = {
|
||||
[CPRMAN_CLOCK_GNRIC] = {
|
||||
.name = "gnric",
|
||||
FILL_CLOCK_MUX_INIT_INFO(GNRIC, unknown),
|
||||
},
|
||||
[CPRMAN_CLOCK_VPU] = {
|
||||
.name = "vpu",
|
||||
.int_bits = 12,
|
||||
.frac_bits = 8,
|
||||
FILL_CLOCK_MUX_INIT_INFO(VPU, core),
|
||||
},
|
||||
[CPRMAN_CLOCK_SYS] = {
|
||||
.name = "sys",
|
||||
FILL_CLOCK_MUX_INIT_INFO(SYS, unknown),
|
||||
},
|
||||
[CPRMAN_CLOCK_PERIA] = {
|
||||
.name = "peria",
|
||||
FILL_CLOCK_MUX_INIT_INFO(PERIA, unknown),
|
||||
},
|
||||
[CPRMAN_CLOCK_PERII] = {
|
||||
.name = "perii",
|
||||
FILL_CLOCK_MUX_INIT_INFO(PERII, unknown),
|
||||
},
|
||||
[CPRMAN_CLOCK_H264] = {
|
||||
.name = "h264",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 8,
|
||||
FILL_CLOCK_MUX_INIT_INFO(H264, core),
|
||||
},
|
||||
[CPRMAN_CLOCK_ISP] = {
|
||||
.name = "isp",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 8,
|
||||
FILL_CLOCK_MUX_INIT_INFO(ISP, core),
|
||||
},
|
||||
[CPRMAN_CLOCK_V3D] = {
|
||||
.name = "v3d",
|
||||
FILL_CLOCK_MUX_INIT_INFO(V3D, core),
|
||||
},
|
||||
[CPRMAN_CLOCK_CAM0] = {
|
||||
.name = "cam0",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 8,
|
||||
FILL_CLOCK_MUX_INIT_INFO(CAM0, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_CAM1] = {
|
||||
.name = "cam1",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 8,
|
||||
FILL_CLOCK_MUX_INIT_INFO(CAM1, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_CCP2] = {
|
||||
.name = "ccp2",
|
||||
FILL_CLOCK_MUX_INIT_INFO(CCP2, unknown),
|
||||
},
|
||||
[CPRMAN_CLOCK_DSI0E] = {
|
||||
.name = "dsi0e",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 8,
|
||||
FILL_CLOCK_MUX_INIT_INFO(DSI0E, dsi0),
|
||||
},
|
||||
[CPRMAN_CLOCK_DSI0P] = {
|
||||
.name = "dsi0p",
|
||||
.int_bits = 0,
|
||||
.frac_bits = 0,
|
||||
FILL_CLOCK_MUX_INIT_INFO(DSI0P, dsi0),
|
||||
},
|
||||
[CPRMAN_CLOCK_DPI] = {
|
||||
.name = "dpi",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 8,
|
||||
FILL_CLOCK_MUX_INIT_INFO(DPI, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_GP0] = {
|
||||
.name = "gp0",
|
||||
.int_bits = 12,
|
||||
.frac_bits = 12,
|
||||
FILL_CLOCK_MUX_INIT_INFO(GP0, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_GP1] = {
|
||||
.name = "gp1",
|
||||
.int_bits = 12,
|
||||
.frac_bits = 12,
|
||||
FILL_CLOCK_MUX_INIT_INFO(GP1, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_GP2] = {
|
||||
.name = "gp2",
|
||||
.int_bits = 12,
|
||||
.frac_bits = 12,
|
||||
FILL_CLOCK_MUX_INIT_INFO(GP2, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_HSM] = {
|
||||
.name = "hsm",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 8,
|
||||
FILL_CLOCK_MUX_INIT_INFO(HSM, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_OTP] = {
|
||||
.name = "otp",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 0,
|
||||
FILL_CLOCK_MUX_INIT_INFO(OTP, xosc),
|
||||
},
|
||||
[CPRMAN_CLOCK_PCM] = {
|
||||
.name = "pcm",
|
||||
.int_bits = 12,
|
||||
.frac_bits = 12,
|
||||
FILL_CLOCK_MUX_INIT_INFO(PCM, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_PWM] = {
|
||||
.name = "pwm",
|
||||
.int_bits = 12,
|
||||
.frac_bits = 12,
|
||||
FILL_CLOCK_MUX_INIT_INFO(PWM, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_SLIM] = {
|
||||
.name = "slim",
|
||||
.int_bits = 12,
|
||||
.frac_bits = 12,
|
||||
FILL_CLOCK_MUX_INIT_INFO(SLIM, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_SMI] = {
|
||||
.name = "smi",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 8,
|
||||
FILL_CLOCK_MUX_INIT_INFO(SMI, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_TEC] = {
|
||||
.name = "tec",
|
||||
.int_bits = 6,
|
||||
.frac_bits = 0,
|
||||
FILL_CLOCK_MUX_INIT_INFO(TEC, xosc),
|
||||
},
|
||||
[CPRMAN_CLOCK_TD0] = {
|
||||
.name = "td0",
|
||||
FILL_CLOCK_MUX_INIT_INFO(TD0, unknown),
|
||||
},
|
||||
[CPRMAN_CLOCK_TD1] = {
|
||||
.name = "td1",
|
||||
FILL_CLOCK_MUX_INIT_INFO(TD1, unknown),
|
||||
},
|
||||
[CPRMAN_CLOCK_TSENS] = {
|
||||
.name = "tsens",
|
||||
.int_bits = 5,
|
||||
.frac_bits = 0,
|
||||
FILL_CLOCK_MUX_INIT_INFO(TSENS, xosc),
|
||||
},
|
||||
[CPRMAN_CLOCK_TIMER] = {
|
||||
.name = "timer",
|
||||
.int_bits = 6,
|
||||
.frac_bits = 12,
|
||||
FILL_CLOCK_MUX_INIT_INFO(TIMER, xosc),
|
||||
},
|
||||
[CPRMAN_CLOCK_UART] = {
|
||||
.name = "uart",
|
||||
.int_bits = 10,
|
||||
.frac_bits = 12,
|
||||
FILL_CLOCK_MUX_INIT_INFO(UART, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_VEC] = {
|
||||
.name = "vec",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 0,
|
||||
FILL_CLOCK_MUX_INIT_INFO(VEC, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_PULSE] = {
|
||||
.name = "pulse",
|
||||
FILL_CLOCK_MUX_INIT_INFO(PULSE, xosc),
|
||||
},
|
||||
[CPRMAN_CLOCK_SDC] = {
|
||||
.name = "sdram",
|
||||
.int_bits = 6,
|
||||
.frac_bits = 0,
|
||||
FILL_CLOCK_MUX_INIT_INFO(SDC, core),
|
||||
},
|
||||
[CPRMAN_CLOCK_ARM] = {
|
||||
.name = "arm",
|
||||
FILL_CLOCK_MUX_INIT_INFO(ARM, unknown),
|
||||
},
|
||||
[CPRMAN_CLOCK_AVEO] = {
|
||||
.name = "aveo",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 0,
|
||||
FILL_CLOCK_MUX_INIT_INFO(AVEO, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_EMMC] = {
|
||||
.name = "emmc",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 8,
|
||||
FILL_CLOCK_MUX_INIT_INFO(EMMC, periph),
|
||||
},
|
||||
[CPRMAN_CLOCK_EMMC2] = {
|
||||
.name = "emmc2",
|
||||
.int_bits = 4,
|
||||
.frac_bits = 8,
|
||||
FILL_CLOCK_MUX_INIT_INFO(EMMC2, unknown),
|
||||
},
|
||||
};
|
||||
|
||||
#undef FILL_CLOCK_MUX_INIT_INFO
|
||||
#undef FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO
|
||||
#undef SRC_MAPPING_INFO_dsi1
|
||||
#undef SRC_MAPPING_INFO_dsi0
|
||||
#undef SRC_MAPPING_INFO_periph
|
||||
#undef SRC_MAPPING_INFO_core
|
||||
#undef SRC_MAPPING_INFO_xosc
|
||||
#undef SRC_MAPPING_INFO_unknown
|
||||
|
||||
static inline void set_clock_mux_init_info(BCM2835CprmanState *s,
|
||||
CprmanClockMuxState *mux,
|
||||
CprmanClockMux id)
|
||||
{
|
||||
mux->id = id;
|
||||
mux->reg_ctl = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset];
|
||||
mux->reg_div = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset + 1];
|
||||
mux->int_bits = CLOCK_MUX_INIT_INFO[id].int_bits;
|
||||
mux->frac_bits = CLOCK_MUX_INIT_INFO[id].frac_bits;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user