target-s390: Convert BRANCH ON CONDITION
Signed-off-by: Richard Henderson <rth@twiddle.net>
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8ac33cdb8b
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7233f2ed17
@ -68,6 +68,12 @@
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/* BRANCH RELATIVE AND SAVE */
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C(0xa705, BRAS, RI_b, Z, 0, 0, r1, 0, basi, 0)
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C(0xc005, BRASL, RIL_b, Z, 0, 0, r1, 0, basi, 0)
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/* BRANCH ON CONDITION */
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C(0x0700, BCR, RR_b, Z, 0, r2_nz, 0, 0, bc, 0)
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C(0x4700, BC, RX_b, Z, 0, a2, 0, 0, bc, 0)
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/* BRANCH RELATIVE ON CONDITION */
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C(0xa704, BRC, RI_c, Z, 0, 0, 0, 0, bc, 0)
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C(0xc004, BRCL, RIL_c, Z, 0, 0, 0, 0, bc, 0)
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/* COMPARE */
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C(0x1900, CR, RR_a, Z, r1_o, r2_o, 0, 0, 0, cmps32)
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@ -1021,35 +1021,6 @@ static void gen_jcc(DisasContext *s, uint32_t mask, int skip)
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free_compare(&c);
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}
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static void gen_bcr(DisasContext *s, uint32_t mask, TCGv_i64 target,
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uint64_t offset)
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{
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int skip;
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if (mask == 0xf) {
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/* unconditional */
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gen_update_cc_op(s);
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tcg_gen_mov_i64(psw_addr, target);
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tcg_gen_exit_tb(0);
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} else if (mask == 0) {
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/* ignore cc and never match */
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gen_goto_tb(s, 0, offset + 2);
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} else {
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TCGv_i64 new_addr = tcg_temp_local_new_i64();
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tcg_gen_mov_i64(new_addr, target);
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skip = gen_new_label();
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gen_jcc(s, mask, skip);
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gen_update_cc_op(s);
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tcg_gen_mov_i64(psw_addr, new_addr);
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tcg_temp_free_i64(new_addr);
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tcg_gen_exit_tb(0);
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gen_set_label(skip);
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tcg_temp_free_i64(new_addr);
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gen_goto_tb(s, 1, offset + 2);
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}
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}
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static void gen_brc(uint32_t mask, DisasContext *s, int32_t offset)
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{
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int skip;
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@ -2595,46 +2566,6 @@ static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1,
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}
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}
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static void disas_c0(CPUS390XState *env, DisasContext *s, int op, int r1, int i2)
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{
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TCGv_i32 tmp32_1, tmp32_2;
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uint64_t target = s->pc + i2 * 2LL;
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int l1;
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LOG_DISAS("disas_c0: op 0x%x r1 %d i2 %d\n", op, r1, i2);
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switch (op) {
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case 0x4: /* BRCL M1,I2 [RIL] */
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if (r1 == 15) { /* m1 == r1 */
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gen_goto_tb(s, 0, target);
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s->is_jmp = DISAS_TB_JUMP;
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break;
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}
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/* m1 & (1 << (3 - cc)) */
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tmp32_1 = tcg_const_i32(3);
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tmp32_2 = tcg_const_i32(1);
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gen_op_calc_cc(s);
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tcg_gen_sub_i32(tmp32_1, tmp32_1, cc_op);
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tcg_gen_shl_i32(tmp32_2, tmp32_2, tmp32_1);
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tcg_temp_free_i32(tmp32_1);
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tmp32_1 = tcg_const_i32(r1); /* m1 == r1 */
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tcg_gen_and_i32(tmp32_1, tmp32_1, tmp32_2);
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l1 = gen_new_label();
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tcg_gen_brcondi_i32(TCG_COND_EQ, tmp32_1, 0, l1);
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gen_goto_tb(s, 0, target);
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gen_set_label(l1);
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gen_goto_tb(s, 1, s->pc + 6);
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s->is_jmp = DISAS_TB_JUMP;
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tcg_temp_free_i32(tmp32_1);
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tcg_temp_free_i32(tmp32_2);
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break;
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default:
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LOG_DISAS("illegal c0 operation 0x%x\n", op);
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gen_illegal_opcode(s);
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break;
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}
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}
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static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
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{
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TCGv_i64 tmp, tmp2, tmp3, tmp4;
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@ -2681,18 +2612,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
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tcg_temp_free_i64(tmp);
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}
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break;
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case 0x7: /* BCR M1,R2 [RR] */
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insn = ld_code2(env, s->pc);
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decode_rr(s, insn, &r1, &r2);
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if (r2) {
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tmp = load_reg(r2);
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gen_bcr(s, r1, tmp, s->pc);
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tcg_temp_free_i64(tmp);
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s->is_jmp = DISAS_TB_JUMP;
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} else {
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/* XXX: "serialization and checkpoint-synchronization function"? */
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}
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break;
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case 0xa: /* SVC I [RR] */
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insn = ld_code2(env, s->pc);
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debug_insn(insn);
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@ -2814,13 +2733,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
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tcg_temp_free_i32(tmp32_1);
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tcg_temp_free_i64(tmp);
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break;
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case 0x47: /* BC M1,D2(X2,B2) [RX] */
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insn = ld_code4(env, s->pc);
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tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
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gen_bcr(s, r1, tmp, s->pc + 4);
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tcg_temp_free_i64(tmp);
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s->is_jmp = DISAS_TB_JUMP;
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break;
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case 0x4e: /* CVD R1,D2(X2,B2) [RX] */
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insn = ld_code4(env, s->pc);
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tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
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@ -3348,13 +3260,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s)
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gen_op_movi_cc(s, 0);
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}
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break;
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case 0xc0:
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insn = ld_code6(env, s->pc);
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r1 = (insn >> 36) & 0xf;
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op = (insn >> 32) & 0xf;
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i2 = (int)insn;
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disas_c0(env, s, op, r1, i2);
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break;
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case 0xd2: /* MVC D1(L,B1),D2(B2) [SS] */
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case 0xd4: /* NC D1(L,B1),D2(B2) [SS] */
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case 0xd5: /* CLC D1(L,B1),D2(B2) [SS] */
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@ -3728,6 +3633,131 @@ static ExitStatus help_goto_direct(DisasContext *s, uint64_t dest)
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}
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}
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static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
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bool is_imm, int imm, TCGv_i64 cdest)
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{
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ExitStatus ret;
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uint64_t dest = s->pc + 2 * imm;
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int lab;
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/* Take care of the special cases first. */
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if (c->cond == TCG_COND_NEVER) {
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ret = NO_EXIT;
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goto egress;
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}
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if (is_imm) {
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if (dest == s->next_pc) {
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/* Branch to next. */
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ret = NO_EXIT;
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goto egress;
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}
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if (c->cond == TCG_COND_ALWAYS) {
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ret = help_goto_direct(s, dest);
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goto egress;
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}
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} else {
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if (TCGV_IS_UNUSED_I64(cdest)) {
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/* E.g. bcr %r0 -> no branch. */
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ret = NO_EXIT;
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goto egress;
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}
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if (c->cond == TCG_COND_ALWAYS) {
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tcg_gen_mov_i64(psw_addr, cdest);
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ret = EXIT_PC_UPDATED;
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goto egress;
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}
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}
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if (use_goto_tb(s, s->next_pc)) {
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if (is_imm && use_goto_tb(s, dest)) {
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/* Both exits can use goto_tb. */
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gen_update_cc_op(s);
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lab = gen_new_label();
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if (c->is_64) {
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tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
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} else {
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tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
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}
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/* Branch not taken. */
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tcg_gen_goto_tb(0);
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tcg_gen_movi_i64(psw_addr, s->next_pc);
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tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
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/* Branch taken. */
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gen_set_label(lab);
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tcg_gen_goto_tb(1);
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tcg_gen_movi_i64(psw_addr, dest);
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tcg_gen_exit_tb((tcg_target_long)s->tb + 1);
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ret = EXIT_GOTO_TB;
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} else {
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/* Fallthru can use goto_tb, but taken branch cannot. */
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/* Store taken branch destination before the brcond. This
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avoids having to allocate a new local temp to hold it.
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We'll overwrite this in the not taken case anyway. */
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if (!is_imm) {
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tcg_gen_mov_i64(psw_addr, cdest);
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}
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lab = gen_new_label();
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if (c->is_64) {
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tcg_gen_brcond_i64(c->cond, c->u.s64.a, c->u.s64.b, lab);
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} else {
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tcg_gen_brcond_i32(c->cond, c->u.s32.a, c->u.s32.b, lab);
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}
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/* Branch not taken. */
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gen_update_cc_op(s);
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tcg_gen_goto_tb(0);
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tcg_gen_movi_i64(psw_addr, s->next_pc);
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tcg_gen_exit_tb((tcg_target_long)s->tb + 0);
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gen_set_label(lab);
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if (is_imm) {
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tcg_gen_movi_i64(psw_addr, dest);
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}
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ret = EXIT_PC_UPDATED;
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}
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} else {
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/* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
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Most commonly we're single-stepping or some other condition that
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disables all use of goto_tb. Just update the PC and exit. */
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TCGv_i64 next = tcg_const_i64(s->next_pc);
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if (is_imm) {
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cdest = tcg_const_i64(dest);
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}
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if (c->is_64) {
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tcg_gen_movcond_i64(c->cond, psw_addr, c->u.s64.a, c->u.s64.b,
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cdest, next);
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} else {
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TCGv_i32 t0 = tcg_temp_new_i32();
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TCGv_i64 t1 = tcg_temp_new_i64();
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TCGv_i64 z = tcg_const_i64(0);
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tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b);
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tcg_gen_extu_i32_i64(t1, t0);
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tcg_temp_free_i32(t0);
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tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next);
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tcg_temp_free_i64(t1);
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tcg_temp_free_i64(z);
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}
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if (is_imm) {
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tcg_temp_free_i64(cdest);
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}
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tcg_temp_free_i64(next);
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ret = EXIT_PC_UPDATED;
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}
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egress:
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free_compare(c);
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return ret;
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}
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/* ====================================================================== */
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/* The operations. These perform the bulk of the work for any insn,
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usually after the operands have been loaded and output initialized. */
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@ -3801,6 +3831,17 @@ static ExitStatus op_basi(DisasContext *s, DisasOps *o)
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return help_goto_direct(s, s->pc + 2 * get_field(s->fields, i2));
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}
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static ExitStatus op_bc(DisasContext *s, DisasOps *o)
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{
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int m1 = get_field(s->fields, m1);
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bool is_imm = have_field(s->fields, i2);
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int imm = is_imm ? get_field(s->fields, i2) : 0;
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DisasCompare c;
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disas_jcc(s, &c, m1);
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return help_branch(s, &c, is_imm, imm, o->in2);
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}
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static ExitStatus op_insi(DisasContext *s, DisasOps *o)
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{
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int shift = s->insn->data & 0xff;
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