Update bochs bios
They have applied all of our patches and they have an additional HPET fix. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6289 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aliguori
parent
429d0a3db8
commit
71ac3b08ae
@ -1,129 +0,0 @@
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From: Izik Eidus <izike@qumranet.com>
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add support to memory above the pci hole
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the new memory region is mapped after address 0x100000000,
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the bios take the size of the memory after the 0x100000000 from
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three new cmos bytes.
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diff --git a/bios/rombios.c b/bios/rombios.c
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index 1be0816..b70f249 100644
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--- a/bios/rombios.c
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+++ b/bios/rombios.c
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@@ -4442,22 +4442,25 @@ BX_DEBUG_INT15("case default:\n");
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#endif // BX_USE_PS2_MOUSE
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-void set_e820_range(ES, DI, start, end, type)
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+void set_e820_range(ES, DI, start, end, extra_start, extra_end, type)
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Bit16u ES;
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Bit16u DI;
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Bit32u start;
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Bit32u end;
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+ Bit8u extra_start;
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+ Bit8u extra_end;
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Bit16u type;
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{
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write_word(ES, DI, start);
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write_word(ES, DI+2, start >> 16);
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- write_word(ES, DI+4, 0x00);
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+ write_word(ES, DI+4, extra_start);
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write_word(ES, DI+6, 0x00);
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end -= start;
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+ extra_end -= extra_start;
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write_word(ES, DI+8, end);
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write_word(ES, DI+10, end >> 16);
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- write_word(ES, DI+12, 0x0000);
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+ write_word(ES, DI+12, extra_end);
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write_word(ES, DI+14, 0x0000);
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write_word(ES, DI+16, type);
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@@ -4470,7 +4473,9 @@ int15_function32(regs, ES, DS, FLAGS)
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Bit16u ES, DS, FLAGS;
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{
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Bit32u extended_memory_size=0; // 64bits long
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+ Bit32u extra_lowbits_memory_size=0;
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Bit16u CX,DX;
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+ Bit8u extra_highbits_memory_size=0;
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BX_DEBUG_INT15("int15 AX=%04x\n",regs.u.r16.ax);
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@@ -4544,11 +4549,18 @@ ASM_END
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extended_memory_size += (1L * 1024 * 1024);
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}
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+ extra_lowbits_memory_size = inb_cmos(0x5c);
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+ extra_lowbits_memory_size <<= 8;
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+ extra_lowbits_memory_size |= inb_cmos(0x5b);
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+ extra_lowbits_memory_size *= 64;
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+ extra_lowbits_memory_size *= 1024;
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+ extra_highbits_memory_size = inb_cmos(0x5d);
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+
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switch(regs.u.r16.bx)
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{
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case 0:
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set_e820_range(ES, regs.u.r16.di,
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- 0x0000000L, 0x0009f000L, 1);
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+ 0x0000000L, 0x0009f000L, 0, 0, 1);
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regs.u.r32.ebx = 1;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4557,7 +4569,7 @@ ASM_END
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break;
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case 1:
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set_e820_range(ES, regs.u.r16.di,
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- 0x0009f000L, 0x000a0000L, 2);
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+ 0x0009f000L, 0x000a0000L, 0, 0, 2);
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regs.u.r32.ebx = 2;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4566,7 +4578,7 @@ ASM_END
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break;
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case 2:
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set_e820_range(ES, regs.u.r16.di,
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- 0x000e8000L, 0x00100000L, 2);
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+ 0x000e8000L, 0x00100000L, 0, 0, 2);
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regs.u.r32.ebx = 3;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4577,7 +4589,7 @@ ASM_END
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#if BX_ROMBIOS32
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set_e820_range(ES, regs.u.r16.di,
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0x00100000L,
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- extended_memory_size - ACPI_DATA_SIZE, 1);
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+ extended_memory_size - ACPI_DATA_SIZE ,0, 0, 1);
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regs.u.r32.ebx = 4;
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#else
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set_e820_range(ES, regs.u.r16.di,
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@@ -4593,7 +4605,7 @@ ASM_END
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case 4:
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set_e820_range(ES, regs.u.r16.di,
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extended_memory_size - ACPI_DATA_SIZE,
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- extended_memory_size, 3); // ACPI RAM
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+ extended_memory_size ,0, 0, 3); // ACPI RAM
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regs.u.r32.ebx = 5;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@@ -4603,7 +4615,20 @@ ASM_END
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case 5:
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/* 256KB BIOS area at the end of 4 GB */
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set_e820_range(ES, regs.u.r16.di,
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- 0xfffc0000L, 0x00000000L, 2);
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+ 0xfffc0000L, 0x00000000L ,0, 0, 2);
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+ if (extra_highbits_memory_size || extra_lowbits_memory_size)
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+ regs.u.r32.ebx = 6;
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+ else
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+ regs.u.r32.ebx = 0;
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+ regs.u.r32.eax = 0x534D4150;
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+ regs.u.r32.ecx = 0x14;
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+ CLEAR_CF();
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+ return;
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+ case 6:
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+ /* Maping of memory above 4 GB */
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+ set_e820_range(ES, regs.u.r16.di, 0x00000000L,
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+ extra_lowbits_memory_size, 1, extra_highbits_memory_size
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+ + 1, 1);
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regs.u.r32.ebx = 0;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@ -1,21 +0,0 @@
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From: Avi Kivity <avi@qumranet.com>
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instead of timing out, wait until all cpus are up
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diff --git a/bios/rombios32.c b/bios/rombios32.c
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index ef98a41..05ba40d 100644
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--- a/bios/rombios32.c
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+++ b/bios/rombios32.c
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@@ -512,7 +512,12 @@ void smp_probe(void)
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sipi_vector = AP_BOOT_ADDR >> 12;
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writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
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+#ifndef BX_QEMU
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delay_ms(10);
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+#else
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+ while (cmos_readb(0x5f) + 1 != readw(&smp_cpus))
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+ ;
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+#endif
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}
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BX_INFO("Found %d cpu(s)\n", readw(&smp_cpus));
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}
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@ -1,190 +0,0 @@
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BOCHS BIOS changes to support HPET in QEMU.
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Signed-off-by Beth Kon <eak@us.ibm.com>
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Index: bochs-2.3.7/bios/acpi-dsdt.dsl
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===================================================================
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--- bochs-2.3.7.orig/bios/acpi-dsdt.dsl 2008-10-15 12:39:14.000000000 -0500
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+++ bochs-2.3.7/bios/acpi-dsdt.dsl 2008-10-28 07:58:40.000000000 -0500
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@@ -159,6 +159,26 @@
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Return (MEMP)
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}
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}
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+#ifdef BX_QEMU
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+ Device(HPET) {
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+ Name(_HID, EISAID("PNP0103"))
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+ Name(_UID, 0)
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+ Method (_STA, 0, NotSerialized) {
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+ Return(0x0F)
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+ }
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+ Name(_CRS, ResourceTemplate() {
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+ DWordMemory(
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+ ResourceConsumer, PosDecode, MinFixed, MaxFixed,
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+ NonCacheable, ReadWrite,
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+ 0x00000000,
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+ 0xFED00000,
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+ 0xFED003FF,
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+ 0x00000000,
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+ 0x00000400 /* 1K memory: FED00000 - FED003FF */
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+ )
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+ })
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+ }
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+#endif
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}
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Scope(\_SB.PCI0) {
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Index: bochs-2.3.7/bios/rombios32.c
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===================================================================
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--- bochs-2.3.7.orig/bios/rombios32.c 2008-10-15 12:39:36.000000000 -0500
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+++ bochs-2.3.7/bios/rombios32.c 2008-11-12 14:41:41.000000000 -0600
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@@ -1087,7 +1087,11 @@
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struct rsdt_descriptor_rev1
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{
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ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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+#ifdef BX_QEMU
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+ uint32_t table_offset_entry [4]; /* Array of pointers to other */
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+#else
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uint32_t table_offset_entry [3]; /* Array of pointers to other */
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+#endif
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/* ACPI tables */
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};
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@@ -1227,6 +1231,32 @@
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#endif
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};
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+#ifdef BX_QEMU
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+/*
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+ * * ACPI 2.0 Generic Address Space definition.
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+ * */
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+struct acpi_20_generic_address {
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+ uint8_t address_space_id;
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+ uint8_t register_bit_width;
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+ uint8_t register_bit_offset;
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+ uint8_t reserved;
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+ uint64_t address;
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+};
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+
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+/*
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+ * * HPET Description Table
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+ * */
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+struct acpi_20_hpet {
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+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
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+ uint32_t timer_block_id;
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+ struct acpi_20_generic_address addr;
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+ uint8_t hpet_number;
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+ uint16_t min_tick;
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+ uint8_t page_protect;
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+};
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+#define ACPI_HPET_ADDRESS 0xFED00000UL
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+#endif
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+
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struct madt_io_apic
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{
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APIC_HEADER_DEF
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@@ -1237,6 +1267,17 @@
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* lines start */
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};
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+#ifdef BX_QEMU
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+struct madt_int_override
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+{
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+ APIC_HEADER_DEF
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+ uint8_t bus; /* Identifies ISA Bus */
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+ uint8_t source; /* Bus-relative interrupt source */
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+ uint32_t gsi; /* GSI that source will signal */
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+ uint16_t flags; /* MPS INTI flags */
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+};
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+#endif
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+
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#include "acpi-dsdt.hex"
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static inline uint16_t cpu_to_le16(uint16_t x)
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@@ -1342,6 +1383,10 @@
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struct facs_descriptor_rev1 *facs;
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struct multiple_apic_table *madt;
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uint8_t *dsdt, *ssdt;
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+#ifdef BX_QEMU
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+ struct acpi_20_hpet *hpet;
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+ uint32_t hpet_addr;
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+#endif
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uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
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uint32_t acpi_tables_size, madt_addr, madt_size;
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int i;
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@@ -1384,10 +1429,21 @@
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madt_addr = addr;
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madt_size = sizeof(*madt) +
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sizeof(struct madt_processor_apic) * smp_cpus +
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+#ifdef BX_QEMU
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+ sizeof(struct madt_io_apic) + sizeof(struct madt_int_override);
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+#else
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sizeof(struct madt_io_apic);
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+#endif
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madt = (void *)(addr);
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addr += madt_size;
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+#ifdef BX_QEMU
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+ addr = (addr + 7) & ~7;
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+ hpet_addr = addr;
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+ hpet = (void *)(addr);
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+ addr += sizeof(*hpet);
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+#endif
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+
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acpi_tables_size = addr - base_addr;
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BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
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@@ -1410,6 +1466,9 @@
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rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
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rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
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rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
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+#ifdef BX_QEMU
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+ rsdt->table_offset_entry[3] = cpu_to_le32(hpet_addr);
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+#endif
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acpi_build_table_header((struct acpi_table_header *)rsdt,
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"RSDT", sizeof(*rsdt), 1);
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@@ -1448,6 +1507,9 @@
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{
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struct madt_processor_apic *apic;
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struct madt_io_apic *io_apic;
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+#ifdef BX_QEMU
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+ struct madt_int_override *int_override;
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+#endif
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memset(madt, 0, madt_size);
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madt->local_apic_address = cpu_to_le32(0xfee00000);
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@@ -1467,10 +1529,34 @@
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io_apic->io_apic_id = smp_cpus;
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io_apic->address = cpu_to_le32(0xfec00000);
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io_apic->interrupt = cpu_to_le32(0);
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+#ifdef BX_QEMU
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+ io_apic++;
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+
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+ int_override = (void *)io_apic;
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+ int_override->type = APIC_XRUPT_OVERRIDE;
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+ int_override->length = sizeof(*int_override);
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+ int_override->bus = cpu_to_le32(0);
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+ int_override->source = cpu_to_le32(0);
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+ int_override->gsi = cpu_to_le32(2);
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+ int_override->flags = cpu_to_le32(0);
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+#endif
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acpi_build_table_header((struct acpi_table_header *)madt,
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"APIC", madt_size, 1);
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}
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+
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+#ifdef BX_QEMU
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+ /* HPET */
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+ memset(hpet, 0, sizeof(*hpet));
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+ /* Note timer_block_id value must be kept in sync with value advertised by
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+ * emulated hpet
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+ */
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+ hpet->timer_block_id = cpu_to_le32(0x8086a201);
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+ hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
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+ acpi_build_table_header((struct acpi_table_header *)hpet,
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+ "HPET", sizeof(*hpet), 1);
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+#endif
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+
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}
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/* SMBIOS entry point -- must be written to a 16-bit aligned address
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@ -1 +1 @@
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370a7e0d8419bc05192d766c11b7221e5ffc0f75
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7342176bb0fa9d6cc63b37f6ac239e3f70b74219
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@ -1,4 +1 @@
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0001_bx-qemu.patch
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0002_e820-high-mem.patch
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0003_smp-startup-poll.patch
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0005_hpet.patch
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BIN
pc-bios/bios.bin
BIN
pc-bios/bios.bin
Binary file not shown.
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