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target-sh4: add prefi, icbi, synco

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(Vladimir Prus)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6013 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-12-13 18:57:37 +00:00
parent a9c43f8ede
commit 71968fa65b
2 changed files with 27 additions and 0 deletions
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7
target-sh4/cpu.h
View File

@ -89,6 +89,10 @@ typedef struct tlb_t {
#define NB_MMU_MODES 2 #define NB_MMU_MODES 2
enum sh_features {
SH_FEATURE_SH4A = 1,
};
typedef struct CPUSH4State { typedef struct CPUSH4State {
int id; /* CPU model */ int id; /* CPU model */
@ -113,6 +117,9 @@ typedef struct CPUSH4State {
/* float point status register */ /* float point status register */
float_status fp_status; float_status fp_status;
/* The features that we should emulate. See sh_features above. */
uint32_t features;
/* Those belong to the specific unit (SH7750) but are handled here */ /* Those belong to the specific unit (SH7750) but are handled here */
uint32_t mmucr; /* MMU control register */ uint32_t mmucr; /* MMU control register */
uint32_t pteh; /* page table entry high register */ uint32_t pteh; /* page table entry high register */

20
target-sh4/translate.c
View File

@ -49,6 +49,7 @@ typedef struct DisasContext {
int memidx; int memidx;
uint32_t delayed_pc; uint32_t delayed_pc;
int singlestep_enabled; int singlestep_enabled;
uint32_t features;
} DisasContext; } DisasContext;
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
@ -206,6 +207,7 @@ typedef struct {
uint32_t pvr; uint32_t pvr;
uint32_t prr; uint32_t prr;
uint32_t cvr; uint32_t cvr;
uint32_t features;
} sh4_def_t; } sh4_def_t;
static sh4_def_t sh4_defs[] = { static sh4_def_t sh4_defs[] = {
@ -227,6 +229,7 @@ static sh4_def_t sh4_defs[] = {
.pvr = 0x10300700, .pvr = 0x10300700,
.prr = 0x00000200, .prr = 0x00000200,
.cvr = 0x71440211, .cvr = 0x71440211,
.features = SH_FEATURE_SH4A,
}, },
}; };
@ -271,6 +274,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model)
env = qemu_mallocz(sizeof(CPUSH4State)); env = qemu_mallocz(sizeof(CPUSH4State));
if (!env) if (!env)
return NULL; return NULL;
env->features = def->features;
cpu_exec_init(env); cpu_exec_init(env);
sh4_translate_init(); sh4_translate_init();
env->cpu_model_str = cpu_model; env->cpu_model_str = cpu_model;
@ -1562,6 +1566,21 @@ static void _decode_opc(DisasContext * ctx)
return; return;
case 0x0083: /* pref @Rn */ case 0x0083: /* pref @Rn */
return; return;
case 0x00d3: /* prefi @Rn */
if (ctx->features & SH_FEATURE_SH4A)
return;
else
break;
case 0x00e3: /* icbi @Rn */
if (ctx->features & SH_FEATURE_SH4A)
return;
else
break;
case 0x00ab: /* synco */
if (ctx->features & SH_FEATURE_SH4A)
return;
else
break;
case 0x4024: /* rotcl Rn */ case 0x4024: /* rotcl Rn */
{ {
TCGv tmp = tcg_temp_new(); TCGv tmp = tcg_temp_new();
@ -1805,6 +1824,7 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
ctx.delayed_pc = -1; /* use delayed pc from env pointer */ ctx.delayed_pc = -1; /* use delayed pc from env pointer */
ctx.tb = tb; ctx.tb = tb;
ctx.singlestep_enabled = env->singlestep_enabled; ctx.singlestep_enabled = env->singlestep_enabled;
ctx.features = env->features;
#ifdef DEBUG_DISAS #ifdef DEBUG_DISAS
if (loglevel & CPU_LOG_TB_CPU) { if (loglevel & CPU_LOG_TB_CPU) {