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RISC-V: Implement atomic mip/sip CSR updates

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Use the new CSR read/modify/write interface to implement
atomic updates to mip/sip.

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Michael Clark 2019-01-04 23:24:04 +00:00 committed by Palmer Dabbelt
parent c7b9517188
commit 71877e2969
No known key found for this signature in database
GPG Key ID: EF4CA1502CCBAB41
1 changed files with 27 additions and 27 deletions
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54
target/riscv/csr.c
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@ -487,25 +487,31 @@ static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
static int read_mip(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = atomic_read(&env->mip);
return 0;
}
static int write_mip(CPURISCVState *env, int csrno, target_ulong val)
static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
target_ulong mask = write_mask & delegable_ints;
uint32_t old_mip;
/*
* csrs, csrc on mip.SEIP is not decomposable into separate read and
* write steps, so a different implementation is needed
*/
/* We can't allow the supervisor to control SEIP as this would allow the
* supervisor to clear a pending external interrupt which will result in
* lost a interrupt in the case a PLIC is attached. The SEIP bit must be
* hardware controlled when a PLIC is attached. This should be an option
* for CPUs with software-delegated Supervisor External Interrupts. */
mask &= ~MIP_SEIP;
qemu_mutex_lock_iothread();
riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP,
(val & (MIP_SSIP | MIP_STIP)));
qemu_mutex_unlock_iothread();
if (mask) {
qemu_mutex_lock_iothread();
old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
qemu_mutex_unlock_iothread();
} else {
old_mip = atomic_read(&env->mip);
}
if (ret_value) {
*ret_value = old_mip;
}
return 0;
}
@ -623,17 +629,11 @@ static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
static int read_sip(CPURISCVState *env, int csrno, target_ulong *val)
static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
*val = atomic_read(&env->mip) & env->mideleg;
return 0;
}
static int write_sip(CPURISCVState *env, int csrno, target_ulong val)
{
target_ulong newval = (atomic_read(&env->mip) & ~env->mideleg)
| (val & env->mideleg);
return write_mip(env, CSR_MIP, newval);
return rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
write_mask & env->mideleg);
}
/* Supervisor Protection and Translation */
@ -812,7 +812,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MEPC] = { read_mepc, write_mepc },
[CSR_MCAUSE] = { read_mcause, write_mcause },
[CSR_MBADADDR] = { read_mbadaddr, write_mbadaddr },
[CSR_MIP] = { read_mip, write_mip },
[CSR_MIP] = { NULL, NULL, rmw_mip },
/* Supervisor Trap Setup */
[CSR_SSTATUS] = { read_sstatus, write_sstatus },
@ -825,7 +825,7 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_SEPC] = { read_sepc, write_sepc },
[CSR_SCAUSE] = { read_scause, write_scause },
[CSR_SBADADDR] = { read_sbadaddr, write_sbadaddr },
[CSR_SIP] = { read_sip, write_sip },
[CSR_SIP] = { NULL, NULL, rmw_sip },
/* Supervisor Protection and Translation */
[CSR_SATP] = { read_satp, write_satp },