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target/riscv: Set VS bits in mideleg for Hyp extension

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Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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Alistair Francis 2020-01-31 17:02:15 -08:00 committed by Palmer Dabbelt
parent 66e594f280
commit 713d8363de
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GPG Key ID: 2E1319F35FBB1889
1 changed files with 3 additions and 0 deletions
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target/riscv/csr.c
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@ -448,6 +448,9 @@ static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
{ {
env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
if (riscv_has_ext(env, RVH)) {
env->mideleg |= VS_MODE_INTERRUPTS;
}
return 0; return 0;
} }