tcg: Introduce TCG_TARGET_HAS_tst_vec
accel/tcg: Init tb size and icount before plugin_gen_tb_end -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmZPazYdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/hkwgAl/Qdaha8HNW+TkbL 3aQU914xSTbQVYKKCihe1R6tJ4jRw9zSj4Bf43f2GCNaz5GZyO2ek3DYHoYF4z/A OzNW1Vg2qQ+DS65EhTrvBWOko70zvTeh4eLyASxgEbCpWmsh1d2oLGO0mdjJkrfe UdcEXPZ+q0iXAWRFChRClYS5eeVnwYfIeOIzdeUgUezA6fD2zyBT5BgJAxgUTm9w jDXJqzcVypDFTSnrBxBVeV2SAVknVM6coc2BoJ/JiVSgupJZuNX7PSbwNI7GTfl/ LfmiAQyhF78KQiK6TqrliK5mr9R0MSyLORcKQQJrh9G+lxxeO4Sd5qw7V21mVhbc YpLJaw== =SJem -----END PGP SIGNATURE----- Merge tag 'pull-tcg-20240523' of https://gitlab.com/rth7680/qemu into staging tcg: Introduce TCG_TARGET_HAS_tst_vec accel/tcg: Init tb size and icount before plugin_gen_tb_end # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmZPazYdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/hkwgAl/Qdaha8HNW+TkbL # 3aQU914xSTbQVYKKCihe1R6tJ4jRw9zSj4Bf43f2GCNaz5GZyO2ek3DYHoYF4z/A # OzNW1Vg2qQ+DS65EhTrvBWOko70zvTeh4eLyASxgEbCpWmsh1d2oLGO0mdjJkrfe # UdcEXPZ+q0iXAWRFChRClYS5eeVnwYfIeOIzdeUgUezA6fD2zyBT5BgJAxgUTm9w # jDXJqzcVypDFTSnrBxBVeV2SAVknVM6coc2BoJ/JiVSgupJZuNX7PSbwNI7GTfl/ # LfmiAQyhF78KQiK6TqrliK5mr9R0MSyLORcKQQJrh9G+lxxeO4Sd5qw7V21mVhbc # YpLJaw== # =SJem # -----END PGP SIGNATURE----- # gpg: Signature made Thu 23 May 2024 09:13:42 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20240523' of https://gitlab.com/rth7680/qemu: accel/tcg: Init tb size and icount before plugin_gen_tb_end tcg/arm: Support TCG_TARGET_HAS_tst_vec tcg/aarch64: Support TCG_TARGET_HAS_tst_vec tcg: Expand TCG_COND_TST* if not TCG_TARGET_HAS_tst_vec tcg: Introduce TCG_TARGET_HAS_tst_vec Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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commit
70581940ca
@ -214,14 +214,14 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
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set_can_do_io(db, true);
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tcg_ctx->emit_before_op = NULL;
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/* May be used by disas_log or plugin callbacks. */
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tb->size = db->pc_next - db->pc_first;
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tb->icount = db->num_insns;
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if (plugin_enabled) {
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plugin_gen_tb_end(cpu, db->num_insns);
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}
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/* The disas_log hook may use these values rather than recompute. */
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tb->size = db->pc_next - db->pc_first;
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tb->icount = db->num_insns;
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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&& qemu_log_in_addr_range(db->pc_first)) {
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FILE *logfile = qemu_log_trylock();
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@ -155,6 +155,7 @@ typedef uint64_t TCGRegSet;
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#define TCG_TARGET_HAS_minmax_vec 0
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#define TCG_TARGET_HAS_bitsel_vec 0
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#define TCG_TARGET_HAS_cmpsel_vec 0
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#define TCG_TARGET_HAS_tst_vec 0
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#else
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#define TCG_TARGET_MAYBE_vec 1
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#endif
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@ -2737,7 +2737,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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TCGCond cond = args[3];
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AArch64Insn insn;
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if (cond == TCG_COND_NE) {
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switch (cond) {
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case TCG_COND_NE:
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if (const_args[2]) {
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if (is_scalar) {
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tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1);
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@ -2752,7 +2753,27 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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}
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tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
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}
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} else {
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break;
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case TCG_COND_TSTNE:
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case TCG_COND_TSTEQ:
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if (const_args[2]) {
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/* (x & 0) == 0 */
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tcg_out_dupi_vec(s, type, MO_8, a0,
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-(cond == TCG_COND_TSTEQ));
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break;
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}
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if (is_scalar) {
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tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a2);
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} else {
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tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a2);
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}
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if (cond == TCG_COND_TSTEQ) {
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tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
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}
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break;
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default:
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if (const_args[2]) {
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if (is_scalar) {
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insn = cmp0_scalar_insn[cond];
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@ -2791,6 +2812,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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}
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tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
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}
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break;
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}
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}
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break;
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@ -167,6 +167,7 @@ typedef enum {
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 1
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#define TCG_TARGET_HAS_cmpsel_vec 0
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#define TCG_TARGET_HAS_tst_vec 1
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_NEED_LDST_LABELS
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@ -2740,17 +2740,33 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_cmp_vec:
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{
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TCGCond cond = args[3];
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ARMInsn insn;
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if (cond == TCG_COND_NE) {
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switch (cond) {
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case TCG_COND_NE:
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if (const_args[2]) {
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tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a1);
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} else {
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tcg_out_vreg3(s, INSN_VCEQ, q, vece, a0, a1, a2);
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tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
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}
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} else {
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ARMInsn insn;
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break;
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case TCG_COND_TSTNE:
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case TCG_COND_TSTEQ:
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if (const_args[2]) {
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/* (x & 0) == 0 */
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tcg_out_dupi_vec(s, type, MO_8, a0,
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-(cond == TCG_COND_TSTEQ));
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break;
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}
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tcg_out_vreg3(s, INSN_VTST, q, vece, a0, a1, a2);
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if (cond == TCG_COND_TSTEQ) {
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tcg_out_vreg2(s, INSN_VMVN, q, 0, a0, a0);
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}
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break;
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default:
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if (const_args[2]) {
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insn = vec_cmp0_insn[cond];
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if (insn) {
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@ -2769,6 +2785,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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tcg_debug_assert(insn != 0);
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}
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tcg_out_vreg3(s, insn, q, vece, a0, a1, a2);
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break;
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}
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}
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return;
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@ -150,6 +150,7 @@ extern bool use_neon_instructions;
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 1
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#define TCG_TARGET_HAS_cmpsel_vec 0
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#define TCG_TARGET_HAS_tst_vec 1
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_NEED_LDST_LABELS
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@ -224,6 +224,7 @@ typedef enum {
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec have_avx512vl
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#define TCG_TARGET_HAS_cmpsel_vec -1
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#define TCG_TARGET_HAS_tst_vec 0
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#define TCG_TARGET_deposit_i32_valid(ofs, len) \
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(((ofs) == 0 && ((len) == 8 || (len) == 16)) || \
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@ -194,6 +194,7 @@ typedef enum {
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 1
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#define TCG_TARGET_HAS_cmpsel_vec 0
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#define TCG_TARGET_HAS_tst_vec 0
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#define TCG_TARGET_DEFAULT_MO (0)
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@ -173,6 +173,7 @@ typedef enum {
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec have_vsx
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#define TCG_TARGET_HAS_cmpsel_vec 0
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#define TCG_TARGET_HAS_tst_vec 0
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#define TCG_TARGET_DEFAULT_MO (0)
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#define TCG_TARGET_NEED_LDST_LABELS
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@ -163,6 +163,7 @@ extern uint64_t s390_facilities[3];
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#define TCG_TARGET_HAS_minmax_vec 1
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#define TCG_TARGET_HAS_bitsel_vec 1
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#define TCG_TARGET_HAS_cmpsel_vec 0
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#define TCG_TARGET_HAS_tst_vec 0
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/* used for function call generation */
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#define TCG_TARGET_STACK_ALIGN 8
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@ -508,9 +508,11 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
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TCGTemp *rt = tcgv_vec_temp(r);
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TCGTemp *at = tcgv_vec_temp(a);
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TCGTemp *bt = tcgv_vec_temp(b);
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TCGTemp *tt = NULL;
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TCGArg ri = temp_arg(rt);
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TCGArg ai = temp_arg(at);
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TCGArg bi = temp_arg(bt);
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TCGArg ti;
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TCGType type = rt->base_type;
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int can;
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@ -518,6 +520,18 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
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tcg_debug_assert(bt->base_type >= type);
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tcg_assert_listed_vecop(INDEX_op_cmp_vec);
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can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
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if (!TCG_TARGET_HAS_tst_vec && is_tst_cond(cond)) {
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tt = tcg_temp_new_internal(type, TEMP_EBB);
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ti = temp_arg(tt);
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vec_gen_3(INDEX_op_and_vec, type, 0, ti, ai, bi);
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at = tt;
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ai = ti;
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bt = tcg_constant_internal(type, 0);
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bi = temp_arg(bt);
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cond = tcg_tst_eqne_cond(cond);
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}
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if (can > 0) {
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vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
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} else {
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@ -526,6 +540,10 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
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tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
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tcg_swap_vecop_list(hold_list);
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}
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if (tt) {
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tcg_temp_free_internal(tt);
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}
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}
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static bool do_op3(unsigned vece, TCGv_vec r, TCGv_vec a,
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