PPC: Add CPU local MMIO regions to MPIC
The MPIC exports a register set for each CPU connected to it. They can all be accessed through specific registers or using a shadow page that is mapped differently depending on which CPU accesses it. This patch implements the shadow map, making it possible for guests to access the CPU local registers using the same address on each CPU. Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf
parent
d751dfb313
commit
704c7e5d0f
110
hw/openpic.c
110
hw/openpic.c
@ -2,6 +2,7 @@
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* OpenPIC emulation
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*
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* Copyright (c) 2004 Jocelyn Mayer
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* 2011 Alexander Graf
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -161,6 +162,16 @@ static inline int test_bit (uint32_t *field, int bit)
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return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0;
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}
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static int get_current_cpu(void)
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{
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return cpu_single_env->cpu_index;
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}
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static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
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int idx);
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static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
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uint32_t val, int idx);
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enum {
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IRQ_EXTERNAL = 0x01,
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IRQ_INTERNAL = 0x02,
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@ -590,18 +601,27 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
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DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
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if (addr & 0xF)
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return;
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addr &= 0xFF;
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switch (addr) {
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case 0x00: /* FREP */
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case 0x40:
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case 0x50:
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case 0x60:
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case 0x70:
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case 0x80:
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case 0x90:
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case 0xA0:
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case 0xB0:
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openpic_cpu_write_internal(opp, addr, val, get_current_cpu());
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break;
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case 0x20: /* GLBC */
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case 0x1000: /* FREP */
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break;
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case 0x1020: /* GLBC */
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if (val & 0x80000000 && opp->reset)
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opp->reset(opp);
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opp->glbc = val & ~0x80000000;
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break;
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case 0x80: /* VENI */
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case 0x1080: /* VENI */
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break;
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case 0x90: /* PINT */
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case 0x1090: /* PINT */
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for (idx = 0; idx < opp->nb_cpus; idx++) {
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if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) {
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DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx);
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@ -615,22 +635,20 @@ static void openpic_gbl_write (void *opaque, target_phys_addr_t addr, uint32_t v
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}
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opp->pint = val;
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break;
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#if MAX_IPI > 0
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case 0xA0: /* IPI_IPVP */
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case 0xB0:
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case 0xC0:
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case 0xD0:
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case 0x10A0: /* IPI_IPVP */
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case 0x10B0:
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case 0x10C0:
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case 0x10D0:
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{
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int idx;
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idx = (addr - 0xA0) >> 4;
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idx = (addr - 0x10A0) >> 4;
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write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP, val);
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}
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break;
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#endif
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case 0xE0: /* SPVE */
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case 0x10E0: /* SPVE */
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opp->spve = val & 0x000000FF;
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break;
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case 0xF0: /* TIFR */
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case 0x10F0: /* TIFR */
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opp->tifr = val;
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break;
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default:
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@ -647,36 +665,43 @@ static uint32_t openpic_gbl_read (void *opaque, target_phys_addr_t addr)
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retval = 0xFFFFFFFF;
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if (addr & 0xF)
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return retval;
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addr &= 0xFF;
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switch (addr) {
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case 0x00: /* FREP */
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case 0x1000: /* FREP */
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retval = opp->frep;
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break;
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case 0x20: /* GLBC */
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case 0x1020: /* GLBC */
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retval = opp->glbc;
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break;
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case 0x80: /* VENI */
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case 0x1080: /* VENI */
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retval = opp->veni;
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break;
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case 0x90: /* PINT */
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case 0x1090: /* PINT */
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retval = 0x00000000;
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break;
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#if MAX_IPI > 0
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case 0xA0: /* IPI_IPVP */
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case 0x40:
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case 0x50:
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case 0x60:
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case 0x70:
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case 0x80:
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case 0x90:
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case 0xA0:
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case 0xB0:
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case 0xC0:
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case 0xD0:
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retval = openpic_cpu_read_internal(opp, addr, get_current_cpu());
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break;
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case 0x10A0: /* IPI_IPVP */
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case 0x10B0:
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case 0x10C0:
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case 0x10D0:
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{
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int idx;
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idx = (addr - 0xA0) >> 4;
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idx = (addr - 0x10A0) >> 4;
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retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP);
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}
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break;
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#endif
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case 0xE0: /* SPVE */
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case 0x10E0: /* SPVE */
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retval = opp->spve;
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break;
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case 0xF0: /* TIFR */
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case 0x10F0: /* TIFR */
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retval = opp->tifr;
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break;
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default:
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@ -794,23 +819,23 @@ static uint32_t openpic_src_read (void *opaque, uint32_t addr)
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return retval;
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}
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static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t val)
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static void openpic_cpu_write_internal(void *opaque, target_phys_addr_t addr,
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uint32_t val, int idx)
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{
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openpic_t *opp = opaque;
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IRQ_src_t *src;
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IRQ_dst_t *dst;
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int idx, s_IRQ, n_IRQ;
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int s_IRQ, n_IRQ;
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DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
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DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx,
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addr, val);
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if (addr & 0xF)
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return;
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addr &= 0x1FFF0;
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idx = addr / 0x1000;
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dst = &opp->dst[idx];
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addr &= 0xFF0;
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switch (addr) {
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#if MAX_IPI > 0
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case 0x40: /* PIPD */
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case 0x40: /* IPIDR */
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case 0x50:
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case 0x60:
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case 0x70:
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@ -852,20 +877,24 @@ static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t v
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}
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}
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static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
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static void openpic_cpu_write(void *opaque, target_phys_addr_t addr, uint32_t val)
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{
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openpic_cpu_write_internal(opaque, addr, val, (addr & 0x1f000) >> 12);
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}
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static uint32_t openpic_cpu_read_internal(void *opaque, target_phys_addr_t addr,
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int idx)
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{
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openpic_t *opp = opaque;
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IRQ_src_t *src;
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IRQ_dst_t *dst;
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uint32_t retval;
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int idx, n_IRQ;
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int n_IRQ;
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DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
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DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr);
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retval = 0xFFFFFFFF;
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if (addr & 0xF)
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return retval;
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addr &= 0x1FFF0;
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idx = addr / 0x1000;
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dst = &opp->dst[idx];
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addr &= 0xFF0;
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switch (addr) {
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@ -925,6 +954,11 @@ static uint32_t openpic_cpu_read (void *opaque, target_phys_addr_t addr)
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return retval;
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}
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static uint32_t openpic_cpu_read(void *opaque, target_phys_addr_t addr)
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{
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return openpic_cpu_read_internal(opaque, addr, (addr & 0x1f000) >> 12);
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}
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static void openpic_buggy_write (void *opaque,
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target_phys_addr_t addr, uint32_t val)
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{
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