target-i386: Decode the VEX prefixes
No actual required uses of these encodings yet. Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -37,6 +37,7 @@
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#define PREFIX_LOCK 0x04
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#define PREFIX_DATA 0x08
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#define PREFIX_ADR 0x10
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#define PREFIX_VEX 0x20
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#ifdef TARGET_X86_64
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#define CODE64(s) ((s)->code64)
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@ -98,6 +99,8 @@ typedef struct DisasContext {
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int code64; /* 64 bit code segment */
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int rex_x, rex_b;
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#endif
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int vex_l; /* vex vector length */
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int vex_v; /* vex vvvv register, without 1's compliment. */
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int ss32; /* 32 bit stack segment */
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CCOp cc_op; /* current CC operation */
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bool cc_op_dirty;
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@ -4264,6 +4267,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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x86_64_hregs = 0;
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#endif
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s->rip_offset = 0; /* for relative ip address */
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s->vex_l = 0;
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s->vex_v = 0;
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next_byte:
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b = cpu_ldub_code(env, s->pc);
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s->pc++;
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@ -4315,6 +4320,63 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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}
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break;
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#endif
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case 0xc5: /* 2-byte VEX */
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case 0xc4: /* 3-byte VEX */
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/* VEX prefixes cannot be used except in 32-bit mode.
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Otherwise the instruction is LES or LDS. */
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if (s->code32 && !s->vm86) {
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static const int pp_prefix[4] = {
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0, PREFIX_DATA, PREFIX_REPZ, PREFIX_REPNZ
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};
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int vex3, vex2 = cpu_ldub_code(env, s->pc);
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if (!CODE64(s) && (vex2 & 0xc0) != 0xc0) {
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/* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
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otherwise the instruction is LES or LDS. */
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break;
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}
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s->pc++;
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/* 4.1.1-4.1.3: No preceeding lock, 66, f2, f3, or rex prefixes. */
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if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ
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| PREFIX_LOCK | PREFIX_DATA)) {
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goto illegal_op;
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}
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#ifdef TARGET_X86_64
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if (x86_64_hregs) {
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goto illegal_op;
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}
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#endif
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rex_r = (~vex2 >> 4) & 8;
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if (b == 0xc5) {
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vex3 = vex2;
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b = cpu_ldub_code(env, s->pc++);
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} else {
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#ifdef TARGET_X86_64
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s->rex_x = (~vex2 >> 3) & 8;
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s->rex_b = (~vex2 >> 2) & 8;
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#endif
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vex3 = cpu_ldub_code(env, s->pc++);
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rex_w = (vex3 >> 7) & 1;
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switch (vex2 & 0x1f) {
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case 0x01: /* Implied 0f leading opcode bytes. */
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b = cpu_ldub_code(env, s->pc++) | 0x100;
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break;
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case 0x02: /* Implied 0f 38 leading opcode bytes. */
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b = 0x138;
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break;
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case 0x03: /* Implied 0f 3a leading opcode bytes. */
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b = 0x13a;
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break;
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default: /* Reserved for future use. */
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goto illegal_op;
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}
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}
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s->vex_v = (~vex3 >> 3) & 0xf;
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s->vex_l = (vex3 >> 2) & 1;
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prefixes |= pp_prefix[vex3 & 3] | PREFIX_VEX;
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}
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break;
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}
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/* Post-process prefixes. */
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@ -5461,13 +5523,11 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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}
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break;
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case 0xc4: /* les Gv */
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if (CODE64(s))
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goto illegal_op;
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/* In CODE64 this is VEX3; see above. */
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op = R_ES;
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goto do_lxx;
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case 0xc5: /* lds Gv */
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if (CODE64(s))
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goto illegal_op;
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/* In CODE64 this is VEX2; see above. */
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op = R_DS;
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goto do_lxx;
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case 0x1b2: /* lss Gv */
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