Split CPUID from op_helper
KVM needs to call CPUID from outside of the TCG code. This patch splits out the CPUID logic into a separate helper that both the op helper and KVM can call. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5626 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aliguori
parent
0650f1ab30
commit
6fd805e1d4
@ -730,6 +730,10 @@ void cpu_smm_update(CPUX86State *env);
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/* will be suppressed */
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void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
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void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx);
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/* used to debug */
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#define X86_DUMP_FPU 0x0001 /* dump FPU state too */
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#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
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@ -1287,3 +1287,169 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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return paddr;
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}
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#endif /* !CONFIG_USER_ONLY */
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void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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{
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/* test if maximum index reached */
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if (index & 0x80000000) {
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if (index > env->cpuid_xlevel)
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index = env->cpuid_level;
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} else {
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if (index > env->cpuid_level)
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index = env->cpuid_level;
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}
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switch(index) {
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case 0:
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*eax = env->cpuid_level;
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*ebx = env->cpuid_vendor1;
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*edx = env->cpuid_vendor2;
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*ecx = env->cpuid_vendor3;
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break;
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case 1:
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*eax = env->cpuid_version;
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*ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
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*ecx = env->cpuid_ext_features;
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*edx = env->cpuid_features;
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break;
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case 2:
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/* cache info: needed for Pentium Pro compatibility */
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*eax = 1;
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*ebx = 0;
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*ecx = 0;
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*edx = 0x2c307d;
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break;
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case 4:
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/* cache info: needed for Core compatibility */
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switch (*ecx) {
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case 0: /* L1 dcache info */
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*eax = 0x0000121;
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*ebx = 0x1c0003f;
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*ecx = 0x000003f;
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*edx = 0x0000001;
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break;
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case 1: /* L1 icache info */
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*eax = 0x0000122;
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*ebx = 0x1c0003f;
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*ecx = 0x000003f;
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*edx = 0x0000001;
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break;
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case 2: /* L2 cache info */
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*eax = 0x0000143;
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*ebx = 0x3c0003f;
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*ecx = 0x0000fff;
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*edx = 0x0000001;
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break;
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default: /* end of info */
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*eax = 0;
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*ebx = 0;
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*ecx = 0;
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*edx = 0;
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break;
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}
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break;
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case 5:
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/* mwait info: needed for Core compatibility */
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*eax = 0; /* Smallest monitor-line size in bytes */
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*ebx = 0; /* Largest monitor-line size in bytes */
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*ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
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*edx = 0;
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break;
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case 6:
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/* Thermal and Power Leaf */
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*eax = 0;
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*ebx = 0;
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*ecx = 0;
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*edx = 0;
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break;
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case 9:
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/* Direct Cache Access Information Leaf */
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*eax = 0; /* Bits 0-31 in DCA_CAP MSR */
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*ebx = 0;
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*ecx = 0;
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*edx = 0;
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break;
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case 0xA:
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/* Architectural Performance Monitoring Leaf */
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*eax = 0;
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*ebx = 0;
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*ecx = 0;
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*edx = 0;
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break;
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case 0x80000000:
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*eax = env->cpuid_xlevel;
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*ebx = env->cpuid_vendor1;
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*edx = env->cpuid_vendor2;
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*ecx = env->cpuid_vendor3;
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break;
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case 0x80000001:
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*eax = env->cpuid_features;
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*ebx = 0;
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*ecx = env->cpuid_ext3_features;
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*edx = env->cpuid_ext2_features;
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break;
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case 0x80000002:
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case 0x80000003:
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case 0x80000004:
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*eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
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*ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
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*ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
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*edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
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break;
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case 0x80000005:
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/* cache info (L1 cache) */
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*eax = 0x01ff01ff;
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*ebx = 0x01ff01ff;
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*ecx = 0x40020140;
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*edx = 0x40020140;
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break;
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case 0x80000006:
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/* cache info (L2 cache) */
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*eax = 0;
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*ebx = 0x42004200;
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*ecx = 0x02008140;
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*edx = 0;
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break;
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case 0x80000008:
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/* virtual & phys address size in low 2 bytes. */
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/* XXX: This value must match the one used in the MMU code. */
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if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
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/* 64 bit processor */
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#if defined(USE_KQEMU)
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*eax = 0x00003020; /* 48 bits virtual, 32 bits physical */
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#else
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/* XXX: The physical address space is limited to 42 bits in exec.c. */
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*eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
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#endif
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} else {
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#if defined(USE_KQEMU)
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*eax = 0x00000020; /* 32 bits physical */
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#else
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if (env->cpuid_features & CPUID_PSE36)
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*eax = 0x00000024; /* 36 bits physical */
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else
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*eax = 0x00000020; /* 32 bits physical */
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#endif
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}
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*ebx = 0;
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*ecx = 0;
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*edx = 0;
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break;
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case 0x8000000A:
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*eax = 0x00000001; /* SVM Revision */
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*ebx = 0x00000010; /* nr of ASIDs */
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*ecx = 0;
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*edx = 0; /* optional features */
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break;
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default:
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/* reserved values: zero */
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*eax = 0;
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*ebx = 0;
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*ecx = 0;
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*edx = 0;
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break;
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}
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}
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@ -1885,171 +1885,15 @@ void helper_single_step(void)
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void helper_cpuid(void)
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{
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uint32_t index;
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uint32_t eax, ebx, ecx, edx;
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helper_svm_check_intercept_param(SVM_EXIT_CPUID, 0);
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index = (uint32_t)EAX;
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/* test if maximum index reached */
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if (index & 0x80000000) {
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if (index > env->cpuid_xlevel)
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index = env->cpuid_level;
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} else {
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if (index > env->cpuid_level)
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index = env->cpuid_level;
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}
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switch(index) {
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case 0:
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EAX = env->cpuid_level;
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EBX = env->cpuid_vendor1;
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EDX = env->cpuid_vendor2;
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ECX = env->cpuid_vendor3;
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break;
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case 1:
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EAX = env->cpuid_version;
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EBX = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
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ECX = env->cpuid_ext_features;
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EDX = env->cpuid_features;
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break;
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case 2:
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/* cache info: needed for Pentium Pro compatibility */
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EAX = 1;
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EBX = 0;
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ECX = 0;
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EDX = 0x2c307d;
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break;
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case 4:
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/* cache info: needed for Core compatibility */
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switch (ECX) {
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case 0: /* L1 dcache info */
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EAX = 0x0000121;
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EBX = 0x1c0003f;
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ECX = 0x000003f;
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EDX = 0x0000001;
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break;
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case 1: /* L1 icache info */
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EAX = 0x0000122;
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EBX = 0x1c0003f;
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ECX = 0x000003f;
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EDX = 0x0000001;
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break;
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case 2: /* L2 cache info */
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EAX = 0x0000143;
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EBX = 0x3c0003f;
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ECX = 0x0000fff;
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EDX = 0x0000001;
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break;
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default: /* end of info */
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EAX = 0;
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EBX = 0;
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ECX = 0;
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EDX = 0;
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break;
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}
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break;
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case 5:
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/* mwait info: needed for Core compatibility */
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EAX = 0; /* Smallest monitor-line size in bytes */
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EBX = 0; /* Largest monitor-line size in bytes */
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ECX = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
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EDX = 0;
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break;
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case 6:
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/* Thermal and Power Leaf */
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EAX = 0;
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EBX = 0;
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ECX = 0;
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EDX = 0;
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break;
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case 9:
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/* Direct Cache Access Information Leaf */
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EAX = 0; /* Bits 0-31 in DCA_CAP MSR */
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EBX = 0;
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ECX = 0;
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EDX = 0;
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break;
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case 0xA:
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/* Architectural Performance Monitoring Leaf */
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EAX = 0;
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EBX = 0;
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ECX = 0;
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EDX = 0;
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break;
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case 0x80000000:
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EAX = env->cpuid_xlevel;
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EBX = env->cpuid_vendor1;
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EDX = env->cpuid_vendor2;
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ECX = env->cpuid_vendor3;
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break;
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case 0x80000001:
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EAX = env->cpuid_features;
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EBX = 0;
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ECX = env->cpuid_ext3_features;
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EDX = env->cpuid_ext2_features;
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break;
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case 0x80000002:
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case 0x80000003:
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case 0x80000004:
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EAX = env->cpuid_model[(index - 0x80000002) * 4 + 0];
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EBX = env->cpuid_model[(index - 0x80000002) * 4 + 1];
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ECX = env->cpuid_model[(index - 0x80000002) * 4 + 2];
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EDX = env->cpuid_model[(index - 0x80000002) * 4 + 3];
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break;
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case 0x80000005:
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/* cache info (L1 cache) */
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EAX = 0x01ff01ff;
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EBX = 0x01ff01ff;
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ECX = 0x40020140;
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EDX = 0x40020140;
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break;
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case 0x80000006:
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/* cache info (L2 cache) */
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EAX = 0;
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EBX = 0x42004200;
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ECX = 0x02008140;
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EDX = 0;
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break;
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case 0x80000008:
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/* virtual & phys address size in low 2 bytes. */
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/* XXX: This value must match the one used in the MMU code. */
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if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
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/* 64 bit processor */
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#if defined(USE_KQEMU)
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EAX = 0x00003020; /* 48 bits virtual, 32 bits physical */
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#else
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/* XXX: The physical address space is limited to 42 bits in exec.c. */
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EAX = 0x00003028; /* 48 bits virtual, 40 bits physical */
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#endif
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} else {
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#if defined(USE_KQEMU)
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EAX = 0x00000020; /* 32 bits physical */
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#else
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if (env->cpuid_features & CPUID_PSE36)
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EAX = 0x00000024; /* 36 bits physical */
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else
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EAX = 0x00000020; /* 32 bits physical */
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#endif
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}
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EBX = 0;
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ECX = 0;
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EDX = 0;
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break;
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case 0x8000000A:
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EAX = 0x00000001; /* SVM Revision */
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EBX = 0x00000010; /* nr of ASIDs */
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ECX = 0;
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EDX = 0; /* optional features */
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break;
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default:
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/* reserved values: zero */
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EAX = 0;
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EBX = 0;
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ECX = 0;
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EDX = 0;
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break;
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}
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cpu_x86_cpuid(env, (uint32_t)EAX, &eax, &ebx, &ecx, &edx);
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EAX = eax;
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EBX = ebx;
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ECX = ecx;
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EDX = edx;
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}
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void helper_enter_level(int level, int data32, target_ulong t1)
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