target-microblaze: Convert pvr-full to a CPU property
Originally the pvr-full PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
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bool dcache_writeback;
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bool endi;
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char *version;
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uint8_t pvr;
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} cfg;
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CPUMBState env;
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@ -130,8 +130,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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qemu_init_vcpu(cs);
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env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
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| PVR0_USE_BARREL_MASK \
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env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
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| PVR0_USE_DIV_MASK \
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| PVR0_USE_HW_MUL_MASK \
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| PVR0_USE_EXC_MASK \
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@ -166,7 +165,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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(cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
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(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
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(cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
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(version_code << 16);
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(version_code << 16) |
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(cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
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env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
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(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
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@ -228,6 +228,7 @@ static Property mb_properties[] = {
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false),
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DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
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DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
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DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -212,7 +212,9 @@ typedef struct CPUMBState CPUMBState;
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/* MSR Reset value PVR mask */
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#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
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#define C_PVR_NONE 0
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#define C_PVR_BASIC 1
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#define C_PVR_FULL 2
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/* CPU flags. */
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@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
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mmu_available = 0;
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if (cpu->cfg.use_mmu) {
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mmu_available = 1;
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if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
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&& (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
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if ((cpu->cfg.pvr == C_PVR_FULL) &&
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(env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
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mmu_available = 0;
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}
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}
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