fsl-imx: add simple RTC emulation for i.MX6 and i.MX7 boards

Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com>
Message-id: 20231216133408.2884-1-n.ostrenkov@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Nikita Ostrenkov 2023-12-19 17:57:50 +00:00 committed by Peter Maydell
parent 6980c31dec
commit 6f9c3aaa34
3 changed files with 94 additions and 10 deletions

View File

@ -13,29 +13,101 @@
*/
#include "qemu/osdep.h"
#include "qemu/bitops.h"
#include "qemu/timer.h"
#include "migration/vmstate.h"
#include "hw/misc/imx7_snvs.h"
#include "qemu/cutils.h"
#include "qemu/module.h"
#include "sysemu/sysemu.h"
#include "sysemu/rtc.h"
#include "sysemu/runstate.h"
#include "trace.h"
#define RTC_FREQ 32768ULL
static const VMStateDescription vmstate_imx7_snvs = {
.name = TYPE_IMX7_SNVS,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT64(tick_offset, IMX7SNVSState),
VMSTATE_UINT64(lpcr, IMX7SNVSState),
VMSTATE_END_OF_LIST()
}
};
static uint64_t imx7_snvs_get_count(IMX7SNVSState *s)
{
uint64_t ticks = muldiv64(qemu_clock_get_ns(rtc_clock), RTC_FREQ,
NANOSECONDS_PER_SECOND);
return s->tick_offset + ticks;
}
static uint64_t imx7_snvs_read(void *opaque, hwaddr offset, unsigned size)
{
trace_imx7_snvs_read(offset, 0);
IMX7SNVSState *s = IMX7_SNVS(opaque);
uint64_t ret = 0;
return 0;
switch (offset) {
case SNVS_LPSRTCMR:
ret = extract64(imx7_snvs_get_count(s), 32, 15);
break;
case SNVS_LPSRTCLR:
ret = extract64(imx7_snvs_get_count(s), 0, 32);
break;
case SNVS_LPCR:
ret = s->lpcr;
break;
}
trace_imx7_snvs_read(offset, ret, size);
return ret;
}
static void imx7_snvs_reset(DeviceState *dev)
{
IMX7SNVSState *s = IMX7_SNVS(dev);
s->lpcr = 0;
}
static void imx7_snvs_write(void *opaque, hwaddr offset,
uint64_t v, unsigned size)
{
const uint32_t value = v;
trace_imx7_snvs_write(offset, v, size);
IMX7SNVSState *s = IMX7_SNVS(opaque);
uint64_t new_value = 0, snvs_count = 0;
if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) {
snvs_count = imx7_snvs_get_count(s);
}
switch (offset) {
case SNVS_LPSRTCMR:
new_value = deposit64(snvs_count, 32, 32, v);
break;
case SNVS_LPSRTCLR:
new_value = deposit64(snvs_count, 0, 32, v);
break;
case SNVS_LPCR: {
s->lpcr = v;
const uint32_t mask = SNVS_LPCR_TOP | SNVS_LPCR_DP_EN;
trace_imx7_snvs_write(offset, value);
if (offset == SNVS_LPCR && ((value & mask) == mask)) {
if ((v & mask) == mask) {
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
}
break;
}
}
if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) {
s->tick_offset += new_value - snvs_count;
}
}
static const struct MemoryRegionOps imx7_snvs_ops = {
@ -59,17 +131,24 @@ static void imx7_snvs_init(Object *obj)
{
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
IMX7SNVSState *s = IMX7_SNVS(obj);
struct tm tm;
memory_region_init_io(&s->mmio, obj, &imx7_snvs_ops, s,
TYPE_IMX7_SNVS, 0x1000);
sysbus_init_mmio(sd, &s->mmio);
qemu_get_timedate(&tm, 0);
s->tick_offset = mktimegm(&tm) -
qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
}
static void imx7_snvs_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->reset = imx7_snvs_reset;
dc->vmsd = &vmstate_imx7_snvs;
dc->desc = "i.MX7 Secure Non-Volatile Storage Module";
}

View File

@ -116,8 +116,8 @@ imx7_gpr_read(uint64_t offset) "addr 0x%08" PRIx64
imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx64
# imx7_snvs.c
imx7_snvs_read(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx32
imx7_snvs_write(uint64_t offset, uint32_t value) "addr 0x%08" PRIx64 "value 0x%08" PRIx32
imx7_snvs_read(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS read: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u"
imx7_snvs_write(uint64_t offset, uint64_t value, unsigned size) "i.MX SNVS write: offset 0x%08" PRIx64 " value 0x%08" PRIx64 " size %u"
# mos6522.c
mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d"

View File

@ -20,7 +20,9 @@
enum IMX7SNVSRegisters {
SNVS_LPCR = 0x38,
SNVS_LPCR_TOP = BIT(6),
SNVS_LPCR_DP_EN = BIT(5)
SNVS_LPCR_DP_EN = BIT(5),
SNVS_LPSRTCMR = 0x050, /* Secure Real Time Counter MSB Register */
SNVS_LPSRTCLR = 0x054, /* Secure Real Time Counter LSB Register */
};
#define TYPE_IMX7_SNVS "imx7.snvs"
@ -31,6 +33,9 @@ struct IMX7SNVSState {
SysBusDevice parent_obj;
MemoryRegion mmio;
uint64_t tick_offset;
uint64_t lpcr;
};
#endif /* IMX7_SNVS_H */