Sparc32: convert sparc32_dma to qdev
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
430c7ec700
commit
6f6260c7d6
@ -21,9 +21,11 @@
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "sparc32_dma.h"
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#include "sun4m.h"
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#include "sysbus.h"
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/* debug DMA */
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//#define DEBUG_DMA
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@ -60,6 +62,7 @@
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typedef struct DMAState DMAState;
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struct DMAState {
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SysBusDevice busdev;
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uint32_t dmaregs[DMA_REGS];
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qemu_irq irq;
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void *iommu;
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@ -242,24 +245,56 @@ static int dma_load(QEMUFile *f, void *opaque, int version_id)
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}
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void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
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void *iommu, qemu_irq **dev_irq, qemu_irq **reset)
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void *iommu, qemu_irq *dev_irq, qemu_irq **reset)
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{
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DMAState *s;
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DeviceState *dev;
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SysBusDevice *s;
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DMAState *d;
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dev = qdev_create(NULL, "sparc32_dma");
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qdev_set_prop_ptr(dev, "iommu_opaque", iommu);
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qdev_init(dev);
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s = sysbus_from_qdev(dev);
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sysbus_connect_irq(s, 0, parent_irq);
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*dev_irq = qdev_get_gpio_in(dev, 0);
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sysbus_mmio_map(s, 0, daddr);
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d = FROM_SYSBUS(DMAState, s);
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*reset = &d->dev_reset;
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return d;
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}
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static void sparc32_dma_init1(SysBusDevice *dev)
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{
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DMAState *s = FROM_SYSBUS(DMAState, dev);
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int dma_io_memory;
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s = qemu_mallocz(sizeof(DMAState));
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s->irq = parent_irq;
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s->iommu = iommu;
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sysbus_init_irq(dev, &s->irq);
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s->iommu = qdev_get_prop_ptr(&dev->qdev, "iommu_opaque");
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dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s);
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cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
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sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
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register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
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register_savevm("sparc32_dma", -1, 2, dma_save, dma_load, s);
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qemu_register_reset(dma_reset, s);
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*dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
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*reset = &s->dev_reset;
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return s;
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qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
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}
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static SysBusDeviceInfo sparc32_dma_info = {
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.init = sparc32_dma_init1,
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.qdev.name = "sparc32_dma",
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.qdev.size = sizeof(DMAState),
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.qdev.props = (DevicePropList[]) {
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{.name = "iommu_opaque", .type = PROP_TYPE_PTR},
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{.name = NULL}
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}
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};
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static void sparc32_dma_register_devices(void)
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{
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sysbus_register_withprop(&sparc32_dma_info);
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}
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device_init(sparc32_dma_register_devices)
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@ -3,7 +3,7 @@
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/* sparc32_dma.c */
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void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
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void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
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void *iommu, qemu_irq *dev_irq, qemu_irq **reset);
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void ledma_memory_read(void *opaque, target_phys_addr_t addr,
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uint8_t *buf, int len, int do_bswap);
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void ledma_memory_write(void *opaque, target_phys_addr_t addr,
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18
hw/sun4m.c
18
hw/sun4m.c
@ -433,7 +433,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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unsigned int i;
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void *iommu, *espdma, *ledma, *nvram;
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qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
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*espdma_irq, *ledma_irq;
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espdma_irq, ledma_irq;
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qemu_irq *esp_reset, *le_reset;
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qemu_irq fdc_tc;
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qemu_irq *cpu_halt;
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@ -537,7 +537,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
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graphic_depth);
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lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
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lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
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nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
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hwdef->nvram_size, 8);
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@ -578,7 +578,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
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esp_init(hwdef->esp_base, 2,
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espdma_memory_read, espdma_memory_write,
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espdma, *espdma_irq, esp_reset);
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espdma, espdma_irq, esp_reset);
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if (hwdef->cs_base)
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cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
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@ -1223,7 +1223,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
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unsigned int i;
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void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
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qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
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*espdma_irq, *ledma_irq;
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espdma_irq, ledma_irq;
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qemu_irq *esp_reset, *le_reset;
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ram_addr_t ram_offset, prom_offset;
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unsigned long kernel_size;
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@ -1315,7 +1315,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
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tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
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graphic_depth);
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lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
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lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
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nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
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hwdef->nvram_size, 8);
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@ -1337,7 +1337,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
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esp_init(hwdef->esp_base, 2,
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espdma_memory_read, espdma_memory_write,
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espdma, *espdma_irq, esp_reset);
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espdma, espdma_irq, esp_reset);
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kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
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RAM_size);
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@ -1443,7 +1443,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
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{
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CPUState *env;
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void *iommu, *espdma, *ledma, *nvram;
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qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
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qemu_irq *cpu_irqs, *slavio_irq, espdma_irq, ledma_irq;
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qemu_irq *esp_reset, *le_reset;
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qemu_irq fdc_tc;
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ram_addr_t ram_offset, prom_offset;
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@ -1528,7 +1528,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
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tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
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graphic_depth);
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lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
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lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
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nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
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hwdef->nvram_size, 2);
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@ -1562,7 +1562,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
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esp_init(hwdef->esp_base, 2,
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espdma_memory_read, espdma_memory_write,
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espdma, *espdma_irq, esp_reset);
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espdma, espdma_irq, esp_reset);
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kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
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RAM_size);
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