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Fixes for s390x host vectors

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Fix for arm ldrd unpredictable case
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Merge tag 'pull-tcg-20220314' of https://gitlab.com/rth7680/qemu into staging

Fixes for s390x host vectors
Fix for arm ldrd unpredictable case

# gpg: Signature made Mon 14 Mar 2022 17:32:44 GMT
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* tag 'pull-tcg-20220314' of https://gitlab.com/rth7680/qemu:
  tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1
  tcg/s390x: Fix tcg_out_dup_vec vs general registers
  tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
  tcg/s390x: Fix tcg_out_dupi_vec vs VGM

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-03-14 18:11:36 +00:00
commit 6f4fe14b46
2 changed files with 19 additions and 5 deletions
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17
tcg/arm/tcg-target.c.inc
View File

@ -1689,8 +1689,21 @@ static void tcg_out_qemu_ld_index(TCGContext *s, MemOp opc,
/* LDRD requires alignment; double-check that. */
if (get_alignment_bits(opc) >= MO_64
&& (datalo & 1) == 0 && datahi == datalo + 1) {
tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
} else if (scratch_addend) {
/*
* Rm (the second address op) must not overlap Rt or Rt + 1.
* Since datalo is aligned, we can simplify the test via alignment.
* Flip the two address arguments if that works.
*/
if ((addend & ~1) != datalo) {
tcg_out_ldrd_r(s, COND_AL, datalo, addrlo, addend);
break;
}
if ((addrlo & ~1) != datalo) {
tcg_out_ldrd_r(s, COND_AL, datalo, addend, addrlo);
break;
}
}
if (scratch_addend) {
tcg_out_ld32_rwb(s, COND_AL, datalo, addend, addrlo);
tcg_out_ld32_12(s, COND_AL, datahi, addend, 4);
} else {

7
tcg/s390x/tcg-target.c.inc
View File

@ -2675,6 +2675,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
if (vece == MO_64) {
return true;
}
src = dst;
}
/*
@ -2715,7 +2716,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
msb = clz32(val);
lsb = 31 - ctz32(val);
}
tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32);
tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_32);
return;
}
} else {
@ -2729,7 +2730,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
msb = clz64(val);
lsb = 63 - ctz64(val);
}
tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64);
tcg_out_insn(s, VRIb, VGM, dst, msb, lsb, MO_64);
return;
}
}
@ -2868,7 +2869,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_bitsel_vec:
tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]);
tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1);
break;
case INDEX_op_cmp_vec: